Table of Contents

• Test Technology Educational Progam (TTEP) Tutorials [doi]
• Program Committee [doi]
• Test Technology Technical Council (TTTC) [doi]
• Acknowledgments [doi]
• Reviewers [doi]
• Awards [doi]
• Steering Committee [doi]
• Organizing Committee [doi]
• Forward [doi]
• The Impacts of Untestable Defects on Transition Fault TestingXijiang Lin, Janusz Rajski. 2-7 [doi]
• Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time BorrowingKun Young Chung, Sandeep K. Gupta. 8-15 [doi]
• Path Delay Fault Simulation on Large Industrial DesignsSuriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty. 16-23 [doi]
• A Scheme for On-Chip Timing CharacterizationRamyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham. 24-29 [doi]
• BIST for Network-on-Chip Interconnect InfrastructuresCristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh. 30-35 [doi]
• Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free AssumptionsVishal Suthar, Shantanu Dutt. 36-43 [doi]
• Session AbstractPhil Nigh. 44 [doi]
• Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency ClockingChunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan. 46-51 [doi]
• PEAKASO: Peak-Temperature Aware Scan-Vector OptimizationMinsik Cho, David Z. Pan. 52-57 [doi]
• A New ATPG Method for Efficient Capture Power Reduction During Scan TestingXiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita. 58-65 [doi]
• Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate ExhaustiveRuifeng Guo, Subhasish Mitra, Enamul Amyeen, JinKyu Lee, Srihari Sivaraj, Srikanth Venkataraman. 66-71 [doi]
• Iterative OPDD Based Signal Probability CalculationAvijit Dutta, Nur A. Touba. 72-77 [doi]
• Silicon Evaluation of Logic Proximity Bridge PatternsEric N. Tran, Vishwashanth Kasulasrinivas, Sreejit Chakravarty. 78-85 [doi]
• Session AbstractRubin A. Parekhji. 86-87 [doi]
• Upper Bounding Fault Coverage by Structural Analysis and Signal MonitoringVishwani D. Agrawal, Soumitra Bose, Vijay Gangaram. 88-93 [doi]
• A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel AttacksJeremy Lee, Mohammad Tehranipoor, Jim Plusquellic. 94-99 [doi]
• Interconnect Testing for Networks on ChipsKhadija Stewart, Spyros Tragoudas. 100-107 [doi]
• An Overview of Failure Mechanisms in Embedded Flash MemoriesO. Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. 108-113 [doi]
• A Built-In Self-Repair Scheme for NOR-Type Flash MemoryYu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu. 114-119 [doi]
• Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access MemoriesGurgen Harutunyan, Valery A. Vardanian, Y. Zorian Zorian. 120-127 [doi]
• Session AbstractCheng-Wen Wu. 128-129 [doi]
• An Error-Oriented Test Methodology to Improve Yield with Error-ToleranceTong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer. 130-135 [doi]
• Early, Accurate and Fast Yield Estimation through Monte Carlo-Alternative Probabilistic Behavioral Analog System SimulationsRasit Onur Topaloglu. 136-142 [doi]
• BIST Pretest of ICs: Risks and BenefitsYoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara. 142-149 [doi]
• Session AbstractBernard Courtois. 150-151 [doi]
• Session AbstractAjay Khoche. 152-153 [doi]
• Session AbstractYervant Zorian, Dennis Wassung. 154-155 [doi]
• Session AbstractErik Chmelar, Edward J. McCluskey. 156-157 [doi]
• Session AbstractPraveen Parvathala. 158-159 [doi]
• Improved Handling of False and Multicycle Paths in ATPGVlado Vorisek, Bruce Swanson, Kun-Han Tsai, Dhiraj Goswami. 160-165 [doi]
• On the Automation of the Test Flow of Complex SoCsDavide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda. 166-171 [doi]
• Improving Gate-Level ATPG by Traversing Concurrent EFSMsGiuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli. 172-179 [doi]
• X-IDDQ: A Novel Defect Detection Technique Using IDDQ DataAshutosh Sharma, Anura P. Jayasumana, Yashwant K. Malaiya. 180-185 [doi]
• Energy Efficient Software-Based Self-Test for Wireless Sensor Network NodesRong Zhang, Zeljko Zilic, Katarzyna Radecka. 186-191 [doi]
• Alternate Electrical Tests for Extracting Mechanical Parameters of MEMS Accelerometer SensorsVishwanath Natarajan, Soumendu Bhattacharya, Abhijit Chatterjee. 192-199 [doi]
• Session AbstractKazumi Hatayama. 200-201 [doi]
• Design Optimization for Robustness to Single Event UpsetsQuming Zhou, Mihir R. Choudhury, Kartik Mohanram. 202-207 [doi]
• Design of Soft Error Resilient Linear Digital Filters Using Checksum-Based Probabilistic Error CorrectionMaryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee. 208-213 [doi]
• Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault ToleranceWenjing Rao, Alex Orailoglu, Ramesh Karri. 214-221 [doi]
• Alternate Loop-Back Diagnostic Tests for Wafer-Level Diagnosis of Modern Wireless Transceivers using Spectral SignaturesGanesh Srinivasan, Abhijit Chatterjee, Friedrich Taenzler. 222-227 [doi]
• RF Front-end System Gain and Linearity Built-in TestQi Wang, Mani Soma. 228-233 [doi]
• Integrated CMOS Power Sensors for RF BIST ApplicationsHsieh-Hung Hsieh, Liang-Hung Lu. 234-239 [doi]
• Session AbstractDavide Appello. 240-241 [doi]
• Modular Compactor of Test ResponsesWojciech Rajski, Janusz Rajski. 242-251 [doi]
• Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular EncodingJinKyu Lee, Nur A. Touba. 252-257 [doi]
• Efficient Fault Collapsing via Generalized Dominance RelationsVishnu C. Vimjam, Michael S. Hsiao. 258-265 [doi]
• A Gate-Level Method for Transistor-Level Bridging Fault DiagnosisXinyue Fan, Will Moore, Camelia Hora, Mario H. Konijnenburg, Guido Gronthoud. 266-271 [doi]
• Parametric Fault Diagnosis for Analog Circuits Using a Bayesian FrameworkFang Liu, Plamen K. Nikolov, Sule Ozev. 272-277 [doi]
• Decision Tree Based Mismatch Diagnosis in Analog CircuitsMingjing Chen, Hosam Haggag, Alex Orailoglu. 278-285 [doi]
• Session AbstractMichael Nicolaidis. 286-287 [doi]
• Session AbstractAjay Khoche, Peter Muhmenthaler. 288-289 [doi]
• Session AbstractAndreas G. Veneris, Yiorgos Makris. 290-291 [doi]
• Session AbstractKee Sup Kim, Mohammad Tehranipoor. 292-293 [doi]
• A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition FaultsHangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy. 294-299 [doi]
• Robust Test Generation for Precise Crosstalk-induced Path Delay FaultsHuawei Li, Pei-Fu Shen, Xiaowei Li. 300-305 [doi]
• Multi-Cycle Sensitizable Transition Delay FaultsJais Abraham, Uday Goel, Arun Kumar. 306-313 [doi]
• A SNDR BIST for Sigma-Delta Analogue-to-Digital ConvertersLuís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro. 314-319 [doi]
• Investigating the Efficiency of Integrator-Based Capacitor Array Testing TechniquesSai Raghuram Durbha, Amit Laknaur, Haibo Wang. 320-325 [doi]
• Functional Test of Field Programmable Analog ArraysTiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell. 326-333 [doi]
• Session AbstractYervant Zorian, Bruce C. Kim. 334-335 [doi]
• Enhanced Timing-Based Transition Delay Testing for Small Delay DefectsRichard Putman, Rahul Gawde. 336-342 [doi]
• Scan Tests with Multiple Fault Activation Cycles for Delay FaultsZhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski. 343-348 [doi]
• Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay TestingAdit D. Singh, Gefu Xu. 349-357 [doi]
• Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura. 358-363 [doi]
• Exploiting Regularity for Inductive Fault AnalysisJason G. Brown, R. D. (Shawn) Blanton. 364-369 [doi]
• SCT: An Approach For Testing and Configuring Nanoscale DevicesReza M. Rad, Mohammad Tehranipoor. 370-377 [doi]
• Session AbstractJames Tschanz. 378-379 [doi]
• Accelerating Diagnostic Fault Simulation Using Z-diagnosis and Concurrent Equivalence IdentificationBharath Seshadri, Xiaoming Yu, Srikanth Venkataraman. 380-385 [doi]
• A Pattern Ordering Algorithm for Reducing the Size of Fault DictionariesPaolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda. 386-391 [doi]
• Dominance Based Analysis for Large Volume Production Fail DiagnosisBharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, Enamul Amyeen, Sudhakar M. Reddy. 392-399 [doi]
• A Period Tracking Based On-Chip Sinusoidal Jitter Extraction TechniqueC.-Y. Kuo, J.-L. Huang. 400-405 [doi]
• Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal TestingHaralampos-G. D. Stratigopoulos, Yiorgos Makris. 406-411 [doi]
• Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal CircuitsHongjoong Shin, Byoungho Kim, Jacob A. Abraham. 412-419 [doi]
• Session AbstractR. Chandramouli. 420-421 [doi]
• Session AbstractRajesh Galivanche, Bob Gottlieb. 422-423 [doi]
• Session AbstractAndré Ivanov. 424-425 [doi]
• Session AbstractAjay Khoche, Mike Rodgers, Pete O Neil. 426 [doi]