Abstract is missing.
- Fast path selection for testing of small delay defects considering path correlationsZijian He, Tao Lv, Huawei Li, Xiaowei Li. 3-8 [doi]
- Identification of critical primitive path delay faults without any path enumerationKyriakos Christou, Maria K. Michael, Stelios Neophytou. 9-14 [doi]
- Path clustering for adaptive testTakumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato. 15-20 [doi]
- Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area costTsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li. 21-26 [doi]
- Bit line coupling memory tests for single-cell fails in SRAMsSandra Irobi, Zaid Al-Ars, Said Hamdioui. 27-32 [doi]
- Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rateJaeyong Chung, Joonsung Park, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo. 33-38 [doi]
- Innovative practices session 1C: Innovative practices in RF testRubin A. Parekhji. 39 [doi]
- Test time reduction using parallel RF test techniquesR. Mittal, Sontakke Sontakke, Rubin A. Parekhji. 40 [doi]
- Density estimation for analog/RF test problem solvingSalvador Mir, Haralampos-G. D. Stratigopoulos, Ahcène Bounceur. 41 [doi]
- Low cost test and tuning of RF circuits and systemsAbhijit Chatterjee, Friedrich Taenzler. 42 [doi]
- A novel hybrid method for SDD pattern grading and selectionKe Peng, Jason Thibodeau, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor. 45-50 [doi]
- Forming multi-cycle tests for delay faults by concatenating broadside testsIrith Pomeranz, Sudhakar M. Reddy. 51-56 [doi]
- An output compression scheme for handling X-states from over-clocked delay testsAdit D. Singh, Chao Han, Xi Qian. 57-62 [doi]
- Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BISTFahad Ahmed, Linda Milor. 63-68 [doi]
- Gate-oxide early-life failure identification using delay shiftsYoung Moon Kim, Tze Wee Chen, Y. Kameda, M. Mizuno, Subhasish Mitra. 69-74 [doi]
- Detecting NBTI induced failures in SRAM core-cellsRenan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Pierre Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine. 75-80 [doi]
- Innovative practices session 2C: Design, fabrication and test of flexible electronicsKwang-Ting Cheng. 81 [doi]
- Design, analysis, and test of low-power and reliable flexible electronicsKwang-Ting Cheng, Tsung-Ching Huang. 82 [doi]
- Fabrication and testing of large-area flexible electronics for displays and sensor arraysW. S. Wong. 83 [doi]
- Overview of flexible electronics from ITRI s viewpointJ. Hu. 84 [doi]
- Impact of multiple input switching on delay test under process variationSean H. Wu, Sreejit Chakravarty, Li-C. Wang. 87-92 [doi]
- Low-power test planning for arbitrary at-speed delay-test clock schemesChristian G. Zoellin, Hans-Joachim Wunderlich. 93-98 [doi]
- Selecting the most relevant structural Fmax for system Fmax correlationJanine Chen, Jing Zeng, Li-C. Wang, Jeff Rearick, Michael Mateja. 99-104 [doi]
- On-the-fly variation tolerant mapping in crossbar nano-architecturesCihan Tunc, Mehdi Baradaran Tahoori. 105-110 [doi]
- Pin-count-aware online testing of digital microfluidic biochipsYang Zhao, Krishnendu Chakrabarty. 111-116 [doi]
- Innovative practices session 3C: Industrial practices of test cost reduction techniques: Impact and design tradeoffsSarveswara Tammali. 123 [doi]
- Industrial practices of test cost reduction: Perspective, current design practicesSarveswara Tammali. 124 [doi]
- Adaptive test delivers wide range of sophisticated test solutionsK. Arnold. 125 [doi]
- Test cost and test power conflicts: EDA perspectiveMokhtar Hirech. 126 [doi]
- Panel 4A: Apprentice - VTS edition: Season 3Kee Sup Kim. 129 [doi]
- Special session 4B: Panel low-power test and noise-aware test: Foes or friends?Ilia Polian. 130 [doi]
- Special session 4C: Thesis research poster sessionHaralampos-G. D. Stratigopoulos. 131 [doi]
- A generic low power scan chain wrapper for designs using scan compressionAmit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi, Rubin A. Parekhji. 135-140 [doi]
- Low-capture-power at-speed testing using partial launch-on-capture test schemeZhen Chen, Dong Xiang. 141-146 [doi]
- Theoretical analysis for low-power test decompression using test-slice duplicationSzu-Pang Mu, Mango Chia-Tso Chao. 147-152 [doi]
- CSER: BISER-based concurrent soft-error resilienceLaung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li. 153-158 [doi]
- Workload-driven selective hardening of control state elements in modern microprocessorsMichail Maniatakos, Yiorgos Makris. 159-164 [doi]
- Scalable and accurate estimation of probabilistic behavior in sequential circuitsChien-Chih Yu, John P. Hayes. 165-170 [doi]
- Innovative practices session 5C: Post-silicon debugSmriti Gupta. 171 [doi]
- At-speed scan test with low switching activityElham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab. 177-182 [doi]
- Low power compression architectureSandeep Bhatia. 183-187 [doi]
- Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testingTomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara. 188-193 [doi]
- Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancySaeed Shamshiri, Kwang-Ting Cheng. 194-199 [doi]
- Evaluating yield and testing impact of sub-wavelength lithographyWing Chiu Tam, R. D. (Shawn) Blanton, Wojciech Maly. 200-205 [doi]
- Defect diagnosis based on DFM guidelinesDongok Kim, Irith Pomeranz, Enamul Amyeen, Srikanth Venkataraman. 206-211 [doi]
- Special session 6C: New topic mixed-signal test impact to SoC commercializationKarim Arabi. 212 [doi]
- Application of signal and noise theory to digital VLSI testingNitin Yogi, Vishwani D. Agrawal. 215-220 [doi]
- On multiple bridging faultsIrith Pomeranz, Sudhakar M. Reddy. 221-226 [doi]
- Reusing NoC-infrastructure for test data compressionViktor Froese, Rüdiger Ibers, Sybille Hellebrand. 227-231 [doi]
- Concurrent autonomous self-test for uncore components in system-on-chipsYanjing Li, Onur Mutlu, Donald S. Gardner, Subhasish Mitra. 232-237 [doi]
- Low-sensitivity to process variations aging sensor for automotive safety-critical applicationsJulio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel Maria Cacho Teixeira, Marcelino B. Santos, João Paulo Teixeira. 238-243 [doi]
- Board-level fault diagnosis using Bayesian inferenceZhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty. 244-249 [doi]
- Innovative practices session 7C: Verification and testing challenges in high-level synthesisSandip Ray, Jayanta Bhadra. 250 [doi]
- The roadblocks to broad adoption of high level synthesisMichael Keating. 251 [doi]
- High level synthesis of a Front End filter and DSP engine for analog to digital conversion - a case studyJ. G. Mena, R. Deken, J. E. Coker, M. S. Johnstone, S. R. Ramirez, P. Frey. 252 [doi]
- Easing the verification bottleneck using high level synthesisD. Varma, D. Mackay, P. Thiruchelvam. 253-254 [doi]
- Special session 8A: TTTC 2010 E. J. McCluskey Best Doctoral Thesis AwardHaralampos-G. D. Stratigopoulos. 257 [doi]
- Special session 8B: New topic MOS/MTJ-hybrid circuit with nonvolatile logic-in-memory architecture and its impactTakahiro Hanyu. 258 [doi]
- Special session 8C: Panel EDA for analog DFT/ATPG - will SoC cost pressures make this a reality?Arani Sinha. 259 [doi]
- On-chip testing of blind and open-sleeve TSVs for 3D IC before bondingPo-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai. 263-268 [doi]
- A structured and scalable test access architecture for TSV-based 3D stacked ICsErik Jan Marinissen, Jouke Verbree, Mario H. Konijnenburg. 269-274 [doi]
- Special session 9B: New topic test facilities and infrastructure in CanadaBozena Kaminska, I. L. McWalter. 281 [doi]
- Innovative practices session 9C: Implications of power delivery network for validation and testingSuriyaprakash Natarajan. 282 [doi]
- Power delivery dynamics and its impact on silicon validationEli Chiprout. 283 [doi]
- Power noise and its impact on production test and validation of SoC devicesKarim Arabi. 285 [doi]
- An ADC/DAC loopback testing methodology by DAC output offsetting and scalingXuan-Lun Huang, Jiun-Lang Huang. 289-294 [doi]
- Calibration-assisted production testing for digitally-calibrated ADCsHsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting Cheng. 295-300 [doi]
- Ordering of analog specification tests based on parametric defect level estimationN. Akkouche, Salvador Mir, Emmanuel Simeu. 301-306 [doi]
- A novel hybrid delay testing scheme with low test power, volume, and timeZhen Chen, Sharad C. Seth, Dong Xiang. 307-312 [doi]
- VDDmin test optimization for overscreening minimization through adaptive scan chain maskingMingjing Chen, Alex Orailoglu. 313-318 [doi]
- Too many faults, too little time on creating test sets for enhanced detection of highly critical faults and defectsYiwen Shi, Wan-Chan Hu, Jennifer Dworak. 319-324 [doi]
- 3D self testing with Spidergon STNoCMarcello Coppola. 327 [doi]
- A holistic approach to accurate tuning of RF systems for large and small multiparameter perturbationsVishwanath Natarajan, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee. 331-336 [doi]
- Concurrent process model and specification cause-effect monitoring using alternate diagnostic signaturesShyam Kumar Devarakond, Shreyas Sen, Soumendu Bhattacharya, Abhijit Chatterjee. 337-342 [doi]
- Multitone digital signal based test for RF receiversMohamad A. Zeidan, Aritra Banerjee, Ranjit Gharpurey, Jacob A. Abraham. 343-348 [doi]
- Special session 11B: Hot topic hardware security: Design, test and verification issuesSwarup Bhunia, Anand Raghunathan. 349 [doi]
- Special session 11C: Hot topic design consideration and silicon evaluation of on-chip monitorsSreejit Chakravarty. 350 [doi]
- Special session 12A: Panel adaptive analog test: Feasibility and opportunities aheadHaralampos-G. D. Stratigopoulos. 353 [doi]
- Special session 12B: Embedded tutorial test and fault tolerance of networks-on-chipMarcelo Lubaszewski, Érika F. Cota. 354 [doi]
- Panel 12C: Apprentice - VTS edition judging sessionKee Sup Kim. 355 [doi]