Abstract is missing.
- A case for multi-level main memoryMagnus Ekman, Per Stenström. 1-8 [doi]
- A compressed memory hierarchy using an indirect index cacheErik G. Hallnor, Steven K. Reinhardt. 9-15 [doi]
- A low cost, multithreaded processing-in-memory systemJay B. Brockman, Shyamkumar Thoziyoor, Shannon K. Kuntz, Peter M. Kogge. 16-22 [doi]
- A localizing directory coherence protocolCollin McCurdy, Charles N. Fischer. 23-29 [doi]
- Micro-architecture techniques in the intel E8870 scalable memory controllerFaye A. Briggs, Suresh Chittor, Kai Cheng. 30-36 [doi]
- Memory coherence activity prediction in commercial workloadsStephen Somogyi, Thomas F. Wenisch, Nikolaos Hardavellas, Jangwoo Kim, Anastassia Ailamaki, Babak Falsafi. 37-45 [doi]
- Cache organizations for clustered microarchitecturesJosé González, Fernando Latorre, Antonio González. 46-55 [doi]
- Understanding the effects of wrong-path memory references on processor performanceOnur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt. 56-64 [doi]
- Scalable cache memory design for large-scale SMT architecturesMuhamed F. Mudawar. 65-71 [doi]
- Evaluating kilo-instruction multiprocessorsMarco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero. 72-79 [doi]
- A study of performance impact of memory controller features in multi-processor server environmentChitra Natarajan, Bruce Christenson, Faye A. Briggs. 80-87 [doi]
- On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of SnortG. Surendra, Subhasis Banerjee, S. K. Nandy. 88-95 [doi]
- Selective main memory compression by identifying program phase changesDoron Nakar, Shlomo Weiss. 96-101 [doi]
- A low-power memory hierarchy for a fully programmable baseband processorWolfgang Raab, Hans-Martin Blüthgen, Ulrich Ramacher. 102-106 [doi]
- An analytical model for software-only main memory compressionIrina Chihaia, Thomas R. Gross. 107-113 [doi]
- Compiler-optimized usage of partitioned memoriesLars Wehmeyer, Urs Helmig, Peter Marwedel. 114-120 [doi]
- SCIMA-SMP: on-chip memory processor architecture for SMPChikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi, Hiroshi Nakamura, Mitsuhisa Sato. 121-128 [doi]
- Addressing mode driven low power data caches for embedded processorsRamesh V. Peri, John Fernando, Ravi Kolagotla. 129-135 [doi]
- The Opie compiler from row-major source to Morton-ordered matricesSteven T. Gabriel, David S. Wise. 136-144 [doi]