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2012

Natural and Flexible Error Recovery for Generated Modular Language EnvironmentsMaartje de Jonge, Lennart C. L. Kats, Emma Soderberg, Eelco Visser. TOPLAS, 34(4), December 2012. [doi]

An Algorithm for Layout Preservation in Refactoring TransformationsMaartje de Jonge, Eelco Visser. SLE 2011:

2011

Secure authentication using dynamic virtual keyboard layoutM. Agarwal, M. Mehra, R. Pawar, D. Shah. icwet 2011: 288-291 [doi]

Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard CellsMassimo Alioto. tvlsi, 19(5):751-762, 2011. [doi]

Brunn: An open source laboratory information system for microplates with a graphical plate layout design processJonathan Alvarsson, Claes Andersson, Ola Spjuth, Rolf Larsson, Jarl E. S. Wikberg. bmcbi, 12:179, 2011. [doi]

Use of Area Layout Information for RSSI-Based Indoor Target Tracking MethodsDaisuke Anzai, Kentaro Yanagihara, Kyesan Lee, Shinsuke Hara. ieicet, 94-B(7):1924-1932, 2011. [doi]

An integrated fuzzy simulation-fuzzy data envelopment analysis algorithm for job-shop layout optimization: The case of injection process with ambiguous dataAli Azadeh, Mohsen Moghaddam, S. M. Asadzadeh, A. Negahban. eor, 214(3):768-779, 2011. [doi]

Mapping communication layouts to network hardware characteristics on massive-scale blue gene systemsPavan Balaji, Rinku Gupta, Abhinav Vishnu, Peter H. Beckman. ife, 26(3-4):247-256, 2011. [doi]

Optimal Cache-Oblivious Mesh LayoutsMichael A. Bender, Bradley C. Kuszmaul, Shang-Hua Teng, Kebin Wang. mst, 48(2):269-296, 2011. [doi]

A Constraint Programming Approach to Automatic Layout Definition for Search ResultsAlessandro Bozzon, Marco Brambilla, Laura Cigardi, Sara Comai. ICWE 2011: 371-374 [doi]

Single row facility layout problem using a permutation-based genetic algorithmDilip Datta, André R. S. Amaral, José Rui Figueira. eor, 213(2):388-394, 2011. [doi]

Lithography Constrained Placement and Post-Placement Layout Optimization for ManufacturabilityNishant Dhumane, Sudheendra K. Srivathsa, Sandip Kundu. isvlsi 2011: 200-205 [doi]

Markov Logic Networks for Document Layout CorrectionStefano Ferilli, Teresa Maria Altomare Basile, Nicola Di Mauro. ieaaie 2011: 275-284 [doi]

Investigating modern layout representations for improved 3d design automationRobert Fischbach, Jens Lienig, Johann Knechtel. glvlsi 2011: 337-342 [doi]

Grids & guides: multi-touch layout and alignment toolsMathias Frisch, Sebastian Kleinau, Ricardo Langner, Raimund Dachselt. CHI 2011: 1615-1618 [doi]

SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAsShahin Golshan, Hessam Kooti, Elaheh Bozorgzadeh. tcad, 30(6):829-840, 2011. [doi]

Constraint-Based Layout-Driven Sizing of Analog CircuitsHusni M. Habal, Helmut Graeb. tcad, 30(8):1089-1102, 2011. [doi]

Hypercubic storage layout and transforms in arbitrary dimensions using GPUs and CUDAKenneth A. Hawick, Daniel P. Playne. concurrency, 23(10):1027-1050, 2011. [doi]

System-in-Package: Electrical and Layout PerspectivesLei He, Shauki Elassaad, Yiyu Shi, Yu Hu, Wei Yao. fteda, 4(4):223-306, 2011. [doi]

Declarative XML-based layout state encoding for managing screen real estate of interactive public displaysTommi Heikkinen, Tomas Lindén, Marko Jurmu, Hannu Kukka, Timo Ojala. percom 2011: 82-87 [doi]

Data Layout Transformation for Stencil Computations on Short-Vector SIMD ArchitecturesThomas Henretty, Kevin Stock, Louis-Noël Pouchet, Franz Franchetti, J. Ramanujam, P. Sadayappan. CC 2011: 225-245 [doi]

A concurrent solution for intra-cell flow path layouts and I/O point locations of cells in a cellular manufacturing systemYing-Chin Ho, Ta-Wei Liao. candie, 60(4):614-634, 2011. [doi]

Simultaneous Layout Migration and Decomposition for Double Patterning TechnologyChin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif. tcad, 30(2):284-294, 2011. [doi]

Image Optimization Algorithm Based on Salient Region and Layout AdjustmentZhen Hua, Yewei Li, Jinjiang Li. jcp, 6(6):1222-1229, 2011. [doi]

Optimal layout and deployment for RFID systemsHan-Pang Huang, Ying-Ting Chang. aei, 25(1):4-10, 2011. [doi]

Applying frame layout to hardware design in FPGA for seamless support of cross calls in CPU-FPGA coupling architectureGiang Nguyen Huong, Yeoul Na, Seon Wook Kim. mam, 35(5):462-472, 2011. [doi]

Psychological Effects of Ambient Illumination Control and Illumination Layout While Viewing Various Video ImagesTakuya Iwanami, Ayano Kikuchi, Keita Hirai, Toshiya Nakaguchi, Norimichi Tsumura, Yoichi Miyake. ieicet, 94-A(2):493-499, 2011. [doi]

Local Memory via Layout RandomizationRadha Jagadeesan, Corin Pitcher, Julian Rathke, James Riely. csfw 2011: 161-174 [doi]

A convex optimisation framework for the unequal-areas facility layout problemIbolya Jankovits, Chaomin Luo, Miguel F. Anjos, Anthony Vannelli. eor, 214(2):199-215, 2011. [doi]

Model analysis of multi-finger MOSFET layout in ring oscillator designBo Jiang, Tian Xia. isqed 2011: 347-352 [doi]

Towards ideal window layouts for multi-party, gaze-aware desktop videoconferencingSasa Junuzovic, Kori Inkpen, Rajesh Hegde, Zhengyou Zhang. graphicsinterface 2011: 119-126 [doi]

Optimizing the Layout of Proportional Symbol MapsGuilherme Kunigami, Pedro Jussieu de Rezende, Cid C. de Souza, Tallys H. Yunes. iccsa 2011: 1-16 [doi]

3D Stacked IC layout considering bond pad density and doubling for manufacturing yield improvementDing-Ming Kwai, Chang-Tzu Lin. isqed 2011: 129-134 [doi]

Construction of a computer-simulated mixed reality environment for virtual factory layout planningJonghwan Lee, Soonhung Han, Jeongsam Yang. cii, 62(1):86-98, 2011. [doi]

Evolutionary optimization of layouts for high density free space optical network linksSteffen Limmer, Dietmar Fey, Ulrich Lohmann, Jürgen Jahns. gecco 2011: 1635-1642 [doi]

On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular CircuitsYi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly. tcad, 30(2):229-241, 2011. [doi]

Interactive Modeling of City Layouts using Layers of Procedural ContentMarkus Lipp, Daniel Scherzer, Peter Wonka, Michael Wimmer. cgf, 30(2):345-354, 2011. [doi]

Layout-aware mismatch modeling for CMOS current sources with D/A converter analysisBo Liu, Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake. isqed 2011: 525-532 [doi]

Compliant fixture layout design using topology optimization methodJie Ma, Michael Yu Wang, Xiangyang Zhu. icra 2011: 3757-3763 [doi]

Virtual Store Layout Effects on Consumer Behaviour: Applying an Environmental Psychology Approach in the Online Travel IndustryEmmanouela Manganari, George J. Siomkos, Irini Rigopoulou, Adam P. Vrechopoulos. intr, 21(3), 2011. [doi]

New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nmRandy W. Mann, Benton H. Calhoun. isqed 2011: 425-430 [doi]

Hi-Trees and Their LayoutKim Marriott, Peter Sbarski, Tim van Gelder, Daniel Prager, Andy Bulka. tvcg, 17(3):290-304, 2011. [doi]

Interactive furniture layout using interior design guidelinesPaul Merrell, Eric Schkufza, Zeyang Li, Maneesh Agrawala, Vladlen Koltun. tog, 30(4):87, 2011. [doi]

Self-aligned double patterning (SADP) layout decompositionMinoo Mirsaeedi, J. Andres Torres, Mohab Anis. isqed 2011: 103-109 [doi]

The Layout for the User-Friendly Manual: Case Study on an Internet Set-Up ManualMomoko Nakatani, Takehiko Ohno, Yurika Katagiri, Ai Nakane, Shuji Hashimoto. hci 2011: 40-45 [doi]

Metrics for the evaluation of news site content layout in large-screen contextsMichael Nebeling, Fabrice Matulic, Moira C. Norrie. CHI 2011: 1511-1520 [doi]

Layout Object Model for Extracting the Schema of Web Query InterfacesTiezheng Nie, Derong Shen, Ge Yu, Yue Kou. apweb 2011: 245-257 [doi]

Optimal wafer cutting in shuttle layout problemsLasse Nisted, David Pisinger, Avri Altman. jco, 22(2):202-216, 2011. [doi]

Fine grain thermal modeling and experimental validation of 3D-ICsOprins, H., Adi Srinivasan, Cupak, M., Cherman, V., Torregiani, C., Stucchi, M., {Van der Plas}, G., Marchal, P., Vandevelde, B., Cheng, E.. mj, 42(4):572-578, April 2011. [doi]

Social Based Layouts for the Increase of Locality in Graph OperationsArnau Prat-Pérez, David Dominguez-Sal, Josep-Lluis Larriba-Pey. dasfaa 2011: 558-569 [doi]

The effects of spatial layout and view control on cognitive processingEric D. Ragan, Alex Endert, Doug A. Bowman, Francis K. H. Quek. CHI 2011: 2005-2010 [doi]

Quantifying the Impact of Layout on Productivity: An Analysis from Robotic-Cell ManufacturingTharanga Rajapakshe, Milind Dawande, Chelliah Sriskandarajah. ior, 59(2):440-454, 2011. [doi]

Formal verification of object layout for c++ multiple inheritanceTahina Ramananandro, Gabriel Dos Reis, Xavier Leroy. POPL 2011: 67-80 [doi]

Using pareto-optimality for solving multi-objective unequal area facility layout problemKazi Shah Nawaz Ripon, Kashif Nizam Khan, Kyrre Glette, Mats Høvin, Jim Torresen. gecco 2011: 681-688 [doi]

A simulated annealing algorithm for solving the bi-objective facility layout problemRamazan Sahin. eswa, 38(4):4460-4465, 2011. [doi]

Employing Aesthetic Principles for Automatic Photo Book LayoutPhilipp Sandhaus, Mohammad Rabbath, Susanne Boll. mmm 2011: 84-95 [doi]

Data Layout for Cache Performance on a Multithreaded ArchitectureSubhradyuti Sarkar, Dean M. Tullsen. thipeac, 3:43-68, 2011. [doi]

A New Placement-Ideal Layout for Multiway Replication Storage SystemPengju Shang, Jun Wang, Huijun Zhu, Peng Gu. TC, 60(8):1142-1156, 2011. [doi]

Speeding Up Network Layout and Centrality Measures for Social Computing GoalsPuneet Sharma, Udayan Khurana, Ben Shneiderman, Max Scharrenbroich, John Locke. sbp 2011: 244-251 [doi]

Layout-aware variation evaluation of analog circuits and its validity on op-amp designsKota Shinohara, Mihoko Hidaka, Jing Li, Qing Dong, Bo Yang, Shigetoshi Nakatake. glvlsi 2011: 247-252 [doi]

A Segment-Level Adaptive Data Layout Scheme for Improved Load Balance in Parallel File SystemsHuaiming Song, Yanlong Yin, Xian-He Sun, Rajeev Thakur, Samuel Lang. ccgrid 2011: 414-423 [doi]

A cost-intelligent application-specific data layout scheme for parallel file systemsHuaiming Song, Yanlong Yin, Yong Chen, Xian-He Sun. hpdc 2011: 37-48 [doi]

Automatic Metro Map Layout Using Multicriteria OptimizationJonathan M. Stott, Peter Rodgers, Juan Carlos Martinez-Ovando, Stephen G. Walker. tvcg, 17(1):101-114, 2011. [doi]

Automatic post-layout flow validation tool for Deep Sub-micron process design kitsPinping Sun, Cole Zemke, Wayne H. Woods, Nick Perez, Hailing Wang, Essam Mina, Barbara Dewitt. isqed 2011: 469-472 [doi]

A sensitivity-aware methodology to improve cell layouts for DFM guidelinesSavithri Sundareswaran, Robert L. Maziasz, Vladimir Rozenfeld, Mikhail Sotnikov, Mukhanov Konstantin. isqed 2011: 431-436 [doi]

A heuristic procedure for the integrated facility layout design and flow assignment problemAli Taghavi, Alper Murat. candie, 61(1):55-63, 2011. [doi]

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ CircuitsKazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi. ieicet, 94-C(3):288-295, 2011. [doi]

Social Network Analysis Layout Algorithm under Ontology ModelPeng Wu, Sikun Li. jsw, 6(7):1321-1328, 2011. [doi]

Mixed non-rectangular block packing for non-Manhattan layout architecturesMeng-Chen Wu, Hung-Ming Chen, Jing-Yang Jou. isqed 2011: 257-262 [doi]

Rapid layout pattern classificationJen-Yi Wuu, Fedor G. Pikus, Andres J. Torres, Malgorzata Marek-Sadowska. aspdac 2011: 781-786 [doi]

ASLOP: A field-access affinity-based structure data layout optimizerJianian Yan, Jiangzhou He, Wenguang Chen, Pen-Chung Yew, Weimin Zheng. chinaf, 54(9):1769-1783, 2011. [doi]

Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route LayoutTadashi Yasufuku, Yasumi Nakamura, Piao Zhe, Makoto Takamiya, Takayasu Sakurai. ieicet, 94-C(6):1072-1075, 2011. [doi]

Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structureS. Yoshimoto, T. Amashita, D. Kozuwa, Taiga Takata, M. Yoshimura, Yusuke Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto. iolts 2011: 151-156 [doi]

DARLS: differencing and merging diagrams using dual view, animation, re-layout, layers and a storyboardLoutfouz Zaman, Ashish Kalra, Wolfgang Stürzlinger. CHI 2011: 1657-1662 [doi]

The effect of animation, dual view, difference layers, and relative re-layout in hierarchical diagram differencingLoutfouz Zaman, Ashish Kalra, Wolfgang Stürzlinger. graphicsinterface 2011: 183-190 [doi]

Lithography-aware layout modification considering performance impactHongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao. isqed 2011: 437-441 [doi]

Directly performance-constrained template-based layout retargeting and optimization for analog integrated circuitsLihong Zhang, Zheng Liu. integration, 44(1):1-11, 2011. [doi]

2010

Table layout performance of document authoring toolsMihai Bilauca, Patrick Healy. DOCENG 2010: 199-202 [doi]

Complexity dichotomy on degree-constrained VLSI layouts with unit-length edgesVinícius G. P. de Sá, Celina M. Herrera de Figueiredo, Guilherme Dias da Fonseca, Raphael Machado. endm, 36:391-398, 2010. [doi]

Reasoning about memory layoutsHolger Gast. fmsd, 37(2-3):141-170, 2010. [doi]

A layout technique for class diagrams to be used in product configuration projectsAnders Haug, Lars Hvam, Niels Henrik Mortensen. cii, 61(5):409-418, 2010. [doi]

Visualizing Multivariate Hierarchic Data Using Enhanced Radial Space-Filling LayoutMing Jia, Ling Li, Erin Boggess, Eve Syrkin Wurtele, Julie A. Dickerson. isvc 2010: 350-360 [doi]

Heuristics for the dynamic facility layout problem with unequal-area departmentsAlan R. McKendall Jr., Artak Hakobyan. eor, 201(1):171-182, 2010. [doi]

An efficient biological pathway layout algorithm combining grid-layout and spring embedder for complicated cellular location informationKaname Kojima, Masao Nagasaki, Satoru Miyano. bmcbi, 11:335, 2010. [doi]

Applying Ant System for solving Unequal Area Facility Layout ProblemsKomarudin, Kuan Yew Wong. eor, 202(3):730-746, 2010. [doi]

Software Cartography: thematic software visualization with consistent layoutAdrian Kuhn, David Erni, Peter Loretan, Oscar Nierstrasz. SMR, 22(3):191-210, 2010. [doi]

Layout Generator for Transistor-Level High-Density Regular CircuitsYi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly. tcad, 29(2):197-210, 2010. [doi]

Total-dose-induced edge effect in SOI NMOS transistors with different layoutsJie Liu, Jicheng Zhou, Hongwei Luo, Xuedong Kong, Yunfei En, Qian Shi, Yujuan He. mr, 50(1):45-47, 2010. [doi]

Computer-generated residential building layoutsPaul Merrell, Eric Schkufza, Vladlen Koltun. tog, 29(6):181, 2010. [doi]

A Genetic Algorithm to Find Pareto-optimal Solutions for the Dynamic Facility Layout Problem with Multiple ObjectivesKazi Shah Nawaz Ripon, Kyrre Glette, Mats Høvin, Jim Torresen. iconip 2010: 642-651 [doi]

PHOTOLAND: a new image layout system using spatio-temporal information in digital photosDong-Sung Ryu, Woo-Keun Chung, Hwan-Gue Cho. SAC 2010: 1884-1891 [doi]

An efficient tabu algorithm for the single row facility layout problemHamed Samarghandi, Kourosh Eshghi. eor, 205(1):98-105, 2010. [doi]

A polyhedral study of triplet formulation for single row facility layout problemSujeevraja Sanjeevi, Kiavash Kianfar. DAM, 158(16):1861-1867, 2010. [doi]

Extensions to STaTS for practical applications of the facility layout problemDaniel Scholz, Florian Jaehn, Andreas Junker. eor, 204(3):463-472, 2010. [doi]

Hierarchically organized layout for visualization of biochemical pathwaysJyh-Jong Tsay, Bo-Liang Wu, Yu-Sen Jeng. artmed, 48(2-3):107-117, 2010. [doi]

Visualizing Image Collections Using High-Entropy Layout DistributionsRuixuan Wang, Stephen J. McKenna, Junwei Han, Annette A. Ward. tmm, 12(8):803-813, 2010. [doi]

Solving facility layout problems using Flexible Bay Structure representation and Ant System algorithmKuan Yew Wong, Komarudin. eswa, 37(7):5523-5527, 2010. [doi]

Effects of color sample display and color sample grouping on screen layout usability for customized product color selectionFong-Gong Wu, Cheih-Ying Chen, Ying-Jye Lee, Rain Chen. chb, 26(1):51-60, 2010. [doi]

Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch MinimizationKun Yuan, Jae-Seok Yang, David Z. Pan. tcad, 29(2):185-196, 2010. [doi]

Emergency repositories network layout model and calculationXiufeng Zuo, Yajie Wang, Qian Ran, Rui Cui. icnc 2010: 2754-2758 [doi]

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