Abdsamad Benkrid - researchr alias

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Viewing Publication 1 - 27 from 27

2013

A statistical framework to minimise and predict the range values of quantisation errors in fixed-point FIR filters architecturesAbdsamad Benkrid, Khaled Benkrid. dsp, 23(1):453-469, 2013. [doi]

2012

A generic computer platform for efficient iris recognitionChris Ponder, Khaled Benkrid, Abdsamad Benkrid. icb 2012: 251-256 [doi]

2009

Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal ExtensionAbdsamad Benkrid, Khaled Benkrid. tvlsi, 17(5):709-722, 2009. [doi]

A Highly Parameterized and Efficient FPGA-Based Skeleton for Pairwise Biological Sequence AlignmentKhaled Benkrid, Ying Liu, Abdsamad Benkrid. tvlsi, 17(4):561-570, 2009. [doi]

An FPGA-Based Web Server for High Performance Biological Sequence AlignmentYing Liu, Khaled Benkrid, Abdsamad Benkrid, Server Kasap. ahs 2009: 361-368 [doi]

2008

HIDE+: A Logic Based Hardware Development EnvironmentAbdsamad Benkrid, Khaled Benkrid. engl, 16(3):460-468, 2008. [doi]

2007

Efficient FPGA hardware development: A multi-language approachKhaled Benkrid, Abdsamad Benkrid, S. Belkacemi. jsa, 53(4):184-209, 2007. [doi]

High Performance Biosequence Database Scanning using FPGAsKhaled Benkrid, Ying Liu, Abdsamad Benkrid. icassp 2007: 361-364 [doi]

Design and Implementation of a Highly Parameterised FPGA-Based Skeleton for Pairwise Biological Sequence AlignmentKhaled Benkrid, Ying Liu, Abdsamad Benkrid. fccm 2007: 275-278 [doi]

2006

Handling finite length signals borders in two-channel multirate filter banks for perfect reconstructionAbdsamad Benkrid, Khaled Benkrid. sigpro, 86(2):375-387, 2006. [doi]

HIDE: A hardware intelligent description environmentKhaled Benkrid, S. Belkacemi, Abdsamad Benkrid. mam, 30(6):283-300, 2006. [doi]

2004

Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAsAbdsamad Benkrid, Khaled Benkrid, Danny Crookes. isvlsi 2004: 222-225 [doi]

2003

Minimisation and prediction of the error dynamic range in finite wordlength FIR based architectures: application to the 2-D orthogonal DWTAbdsamad Benkrid, Khaled Benkrid, Danny Crookes. isspa 2003: 283-286 [doi]

A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAsAbdsamad Benkrid, Khaled Benkrid, Danny Crookes. fccm 2003: 273-275 [doi]

An FPGA-Based Image Connected Component LabellerKhaled Benkrid, S. Sukhsawas, Danny Crookes, Abdsamad Benkrid. fpl 2003: 1012-1015 [doi]

A novel approach for diminishing and predicting the error dynamic range in finite wordlength FIR based architecturesAbdsamad Benkrid, Khaled Benkrid, Danny Crookes. icassp 2003: 581-584 [doi]

Design framework for the implementation of the 2-D orthogonal discrete wavelet transform on FPGAAbdsamad Benkrid, Danny Crookes, Khaled Benkrid. fpga 2003: 238 [doi]

Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAsAbdsamad Benkrid, Khaled Benkrid, Danny Crookes. fpl 2003: 553-564 [doi]

Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGAAbdsamad Benkrid, Khaled Benkrid, Danny Crookes. fccm 2003: 162-172 [doi]

2002

2001

High Level Programming for FPGA Based Image and Video Processing Using Hardware SkeletonsKhaled Benkrid, Danny Crookes, J. Smith, Abdsamad Benkrid. fccm 2001: 219-226 [doi]

Design and Implementation of a Generic 2-D Biorthogonal Discrete Wavelet Transform on an FPGAAbdsamad Benkrid, Danny Crookes, Khaled Benkrid. fccm 2001: 190-198 [doi]

2000

High level programming for real time FPGA based video processingKhaled Benkrid, Danny Crookes, J. Smith, Abdsamad Benkrid. icassp 2000: 3227-3230 [doi]

1998

An Environment for Generating FPGA Architectures for Image Algebra-based AlgorithmsDanny Crookes, Khalid Alotaibi, Ahmed Bouridane, Paul Donachy, Abdsamad Benkrid. icip 1998: 990-994

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