Abhaya Asthana - researchr alias

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Viewing Publication 1 - 33 from 33

2023

Finding Needle in a Haystack: An Algorithm for Real-Time Log Anomaly Detection with Real-Time LearningPrachi Chitnis, Abhaya Asthana. issre 2023: 142-147 [doi]

2021

Design, implementation, and evaluation of learning algorithms for dynamic real-time network monitoringRashid Mijumbi, Abhaya Asthana, Markku Koivunen, Fu Haiyong, Qinjun Zhu. ijnm, 31(4), 2021. [doi]

2019

MAYOR: Machine Learning and Analytics for Automated Operations and RecoveryRashid Mijumbi, Abhaya Asthana, Carlos Bernal, Manuel Castejón. icccn 2019: 1-9 [doi]

2018

DARN: Dynamic Baselines for Real-time Network MonitoringRashid Mijumbi, Abhaya Asthana, Markku Koivunen, Fu Haiyong, Zhu Norman. netsoft 2018: 37-45 [doi]

Recent Advances in Software Reliability AssuranceRashid Mijumbi, Kazuhira Okumoto, Abhaya Asthana, Jacques Meekel. issre 2018: 77-82 [doi]

2017

BRACE: Cloud-Based Software Reliability AssuranceKazuhira Okumoto, Abhaya Asthana, Rashid Mijumbi. issre 2017: 57-60 [doi]

2012

Integrative Software Design for Reliability: Beyond Models and Defect PredictionAbhaya Asthana, Kazu Okumoto. bell, 17(3):37-59, 2012. [doi]

2010

End-to-end service availability support: Theory and applicationAbhaya Asthana, Robert S. Blake, Richard D. Jordan, Reza Shafie-Khorasani, Daryl J. Steen. bell, 15(1):149-173, 2010. [doi]

2006

End-to-end availability considerations for services over IMSAbhaya Asthana, Eric J. Bauer, Meenakshi Sharma, Xuemei Zhang. bell, 11(3):199-210, 2006. [doi]

Analyzing network availability of a mobile data network: A case studyBernard L. Malone III, Abhaya Asthana. bell, 11(3):47-56, 2006. [doi]

2000

Hybrid network managementHarvey I. Epstein, Abhaya Asthana, Stephen A. Corum, Leen Mak. bell, 5(4):63-79, 2000. [doi]

1997

A Parallel Architecture for Network Control and Mobility Tracking in Wireless SystemsAbhaya Asthana, Paul Krzyzanowski. wpc, 4(2):237-256, 1997. [doi]

Kaleido: An Environment for Composing Networked Multimedia ApplicationsAbhaya Asthana, James Sienicki, Mani B. Srivastava. hpdc 1997: 181-190 [doi]

Logic-enhanced memory for high performance databasesAbhaya Asthana, Nandit Soparkar, H. V. Jagadish, Paul Krzyzanowski. kes 1997: 517-524 [doi]

1996

An Experimental Active-Memory-Based I/O SubsystemAbhaya Asthana, Mark Cravatts, Paul Krzyzanowski. In Ravi Jain, John Werth, James C. Browne, editors, Input/Output in Parallel and Distributed Computer Systems. pages 373-390, Kluwer/Springer, 1996. [doi]

1995

Run-Time Parallelization of Sequential Database ProgramsNandit Soparkar, Paul Krzyzanowski, H. V. Jagadish, Abhaya Asthana. CIKM 1995: 74-81 [doi]

1994

A Memory Participative Architecture for High Performance Communication SystemsAbhaya Asthana, Paul Krzyzanowski. infocom 1994: 167-174

SEMU: A Parallel Processing System for Timing Simulation of Digital CMOS VLSI CircuitsAbhaya Asthana, Mike Laznovsky, Boyd Mathews. vlsid 1994: 33-38

Towards a Programming Environment for a Computer with Intelligent MemoryAbhaya Asthana, Mark Cravatts, Paul Krzyzanowski. ifipPACT 1994: 89-98

SWIM Active Memory: Architecture and ApplicationsAbhaya Asthana, Mark Cravatts, Paul Krzyzanowski. ifip11-9 1994: 183-188

An Experimental Active-Memory-Based Network EnvironmentAbhaya Asthana, Mark Cravatts, Paul Krzyzanowski. hpdc 1994: 139-146

An Indoor Wireless System for Personalized Shopping AssistanceAbhaya Asthana, Mark Crauatts, Paul Krzyzanowski. wmcsa 1994: 69-74 [doi]

An experimental active memory based I/O subsystemAbhaya Asthana, Mark Cravatts, Paul Krzyzanowski. sigarch, 22(4):29-34, 1994. [doi]

1992

Towards a Gigabit IP RouterAbhaya Asthana, Catherine Delph, H. V. Jagadish, Paul Krzyzanowski. jhsn, 1(4):281-288, 1992. [doi]

1991

The Design of a Back-end Object Management SystemAbhaya Asthana, H. V. Jagadish, Paul Krzyzanowski. Dagstuhl 1991: 294-319

1989

The Architecture of Massively Parallel Numeric ProcessorAbhaya Asthana, Cheryl J. Briggs, Mark R. Cravats, Boyd Mathews. ifip 1989: 891-891

Impact of Advanced VLSI Packaging on the Design of a Large Parallel ComputerAbhaya Asthana, H. V. Jagadish, Boyd Mathews. icpp 1989: 323-327

An Intelligent Memory Transaction EngineAbhaya Asthana, H. V. Jagadish, Scott C. Knauer. mammo 1989: 286-300

1988

1982

A Multi-Microprocessor Architecture with Hardware Support for Communication and SchedulingSudhir Ahuja, Abhaya Asthana. asplos 1982: 205-209

1978

Design and Control of a Three-Stage Switch Matrix in the Presence of Fan-OutAbhaya Asthana. TC, 27(10):886-895, 1978.

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