Artur Chojnacki - researchr alias

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Viewing Publication 1 - 13 from 13

2008

High-Quality Circuit Synthesis for Modern TechnologiesLech Józwiak, Artur Chojnacki, Aleksander Slusarczyk. isqed 2008: 168-173 [doi]

2005

Information-driven circuit synthesis with the pre-characterized gate librariesLech Józwiak, Szymon Bieganski, Artur Chojnacki. jsa, 51(6-7):405-423, 2005. [doi]

2003

Fast and compact sequential circuits for the FPGA-based reconfigurable systemsLech Józwiak, Aleksander Slusarczyk, Artur Chojnacki. jsa, 49(4-6):227-246, 2003. [doi]

Effective and efficient FPGA synthesis through general functional decompositionLech Józwiak, Artur Chojnacki. jsa, 49(4-6):247-265, 2003. [doi]

Information-driven Library-based Circuit SynthesisLech Józwiak, Szymon Bieganski, Artur Chojnacki. dsdm 2003: 148-157 [doi]

2001

2000

Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships MeasuresArtur Chojnacki, Lech Józwiak. ismvl 2000: 83-90 [doi]

1999

Functional Decomposition based on Information Relationship Measures Extremely Effective and Efficient for Symmetric FunctionsLech Józwiak, Artur Chojnacki. euromicro 1999: 1150-1160 [doi]

1998

Application of the Information Measures to Input Support Selection in Functional DecompositionMariusz Rawski, Lech Józwiak, Artur Chojnacki. rsctc 1998: 573-580 [doi]

Efficient Logic Synthesis for FPGAs with Functional Decomposition Based on Information Relationship MeasureMariusz Rawski, Tadeusz Luba, Lech Józwiak, Artur Chojnacki. euromicro 1998: 10008-10015 [doi]

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