Atsushi Kamo - researchr alias

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Viewing Publication 1 - 7 from 7

2005

Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuitsTakashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai. iscas 2005: 4903-4906 [doi]

2004

Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed CircuitsTakashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai. date 2004: 1327-1333 [doi]

2002

An Efficient Simulator for Multiport Interconnects with Model Order Reduction TechniqueHidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai. ieiceta, 85-A(6):1214-1219, 2002. [doi]

A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-DomainKenichi Suzuki, Mitsuhiro Takeda, Atsushi Kamo, Hideki Asai. ieiceta, 85-A(2):395-398, 2002. [doi]

2001

Simulation for the optimal placement of decoupling capacitors on printed circuit boardAtsushi Kamo, Takayuki Watanabe, A. Asai. iscas 2001: 727-730 [doi]

High-speed interconnect simulation using MIMO type of adaptive least square methodMasaya Suzuki, H. Miyashita, Atsushi Kamo, Takayuki Watanabe, Hideki Asai. iscas 2001: 327-330 [doi]

1998

Neural network simulator for spatiotemporal pattern analysisAtsushi Kamo, Hiroshi Ninomiya, Teru Yoneyama, Hideki Asai. icecsys 1998: 109-112 [doi]

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