Burhan Khurshid - researchr alias

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Viewing Publication 1 - 10 from 10

2021

An Efficient Fixed-Point Multiplier Based on CORDIC AlgorithmBurhan Khurshid, Javeed Jeelani Khan. jcsc, 30(5), 2021. [doi]

2018

Improved Synthesis of Generalized Parallel Counters on FPGAs Using Only LUTsBurhan Khurshid. jcsc, 27(1):1-18, 2018. [doi]

2017

LUT based realization of fixed-point multipliers targeting state-of-art FPGAsBurhan Khurshid. dafes, 21(2):89-115, 2017. [doi]

Technology-Optimized Fixed-Point Bit-Parallel Multipliers for FPGAsBurhan Khurshid. vlsisp, 89(2):293-317, 2017. [doi]

Efficient Realization of Fixed-Point Binary and Ternary Adders on FPGAsBurhan Khurshid, Roohie Naaz Mir. jcsc, 26(4):1-29, 2017. [doi]

An Efficient FIR Filter Structure Based on Technology-Optimized Multiply-Adder Unit Targeting LUT-Based FPGAsBurhan Khurshid, Roohie Naaz Mir. cssp, 36(2):600-639, 2017. [doi]

2016

Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAsBurhan Khurshid, Roohie Naaz Mir. ijhpsa, 6(1):28-35, 2016. [doi]

2015

High Efficiency Generalized Parallel Counters for Xilinx FPGAsBurhan Khurshid, Roohie Naaz Mir. hipc 2015: 40-46 [doi]

High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAsBurhan Khurshid, Roohie Naaz Mir. ijrc, 2015, 2015. [doi]

2014

A Hardware Intensive Approach for Efficient Implementation of Numerical Integration for FPGA PlatformsBurhan Khurshid, Roohie Naz Mir. vlsid 2014: 312-317 [doi]

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