Chong S. Rim - researchr alias

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Viewing Publication 1 - 11 from 11

2010

Adaptive Mixed Scheduling for Correcting Errors in Trapping Sets of LDPC CodesSaejoon Kim, Seunghyuk Lee, Jun Heo, Chong S. Rim. icl, 14(7):664-666, 2010. [doi]

1999

SEGRA: a very fast general area router for multichip modulesYoung-Jun Cha, Chong S. Rim, Kazuo Nakajima. tcad, 18(5):659-665, 1999. [doi]

Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boardsYhonkyong Choi, Chong S. Rim. cicc 1999: 571-574 [doi]

A Graph Theoretical Approach for the Yield Enhancement of Reconfigurable VLSI/WSI ArraysJagannathan Narasimhan, Kazuo Nakajima, Chong S. Rim. DAM, 90(1-3):195-221, 1999. [doi]

1997

A simple and effective greedy multilayer router for MCMsYoung-Jun Cha, Chong S. Rim, Kazuo Nakajima. ispd 1997: 67-72 [doi]

1995

A Block Matching Algorithm with 16: 1 Subsampling and Its Hardware DesignYanghoon Kim, Chong S. Rim, Byoungki Min. iscas 1995: 613-616

1994

Automatic Functional Cell Generation in the Sea-of-Gates Layout StyleYhonkyong Choi, Juhyun Lee, Chong S. Rim. iscas 1994: 189-192

Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placementsJ. Narasimham, Kazuo Nakajima, Chong S. Rim, Anton T. Dahbura. tcad, 13(8):976-986, 1994. [doi]

1992

General Circular Permutation LayoutRuey-Der Lou, Majid Sarrafzadeh, Chong S. Rim, Kazuo Nakajima, Sumio Masuda. mst, 25(4):269-292, 1992.

1989

Graph Bipartization and via MinimizationHyeong-Ah Choi, Kazuo Nakajima, Chong S. Rim. siamdm, 2(1):38-47, 1989.

Exact algorithms for multilayer topological via minimizationChong S. Rim, Toshinobu Kashiwabara, Kazuo Nakajima. tcad, 8(11):1165-1173, 1989. [doi]

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