Claudia Feregrino - researchr alias

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Viewing Publication 1 - 11 from 11

2021

A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor NetworksMiguel Morales-Sandoval, Luis Armando Rodriguez Flores, René Cumplido, Jose Juan Garcia Hernandez, Claudia Feregrino, Ignacio Algredo-Badillo. js, 2021, 2021. [doi]

2019

Guest Editorial: Special Issue on Reconfigurable Computing and FPGA TechnologyRené Cumplido, Maya Gokhale, Claudia Feregrino, Michael Hübner. jpdc, 133:359-361, 2019. [doi]

2015

Frequent Itemsets Mining in Data Streams Using Reconfigurable HardwareLázaro Bustio, René Cumplido, Raudel Hernández, José M. Bande, Claudia Feregrino. pkdd 2016: 32-45 [doi]

2012

2006

On the Design and Implementation of a High Performance Configurable Architecture for Testor IdentificationRené Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino. ciarp 2006: 665-673 [doi]

2001

X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data CompressorJose Luis Nunez, Claudia Feregrino, Simon Jones, Stephen Bateman. fpl 2001: 613-617 [doi]

FPGA-Based Modelling Unit for High Speed Lossless Arithmetic CodingRiad Stefo, Jose Luis Nunez, Claudia Feregrino, Sudipta Mahapatra, Simon Jones. fpl 2001: 643-647 [doi]

1999

The X-MatchLITE FPGA-Based Data CompressorJose Luis Nunez, Claudia Feregrino, Simon Jones, Stephen Bateman. euromicro 1999: 1126-1132 [doi]

The X-MatchLITE FPGA-Based Data CompressorJose Luis Nunez, Claudia Feregrino, Stephen Bateman, Simon Jones. fpga 1999: 255 [doi]

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