Dilip K. Banerji - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 29 from 29

2009

Meta-Heuristic Based Techniques for FPGA Placement: A StudyShawki Areibi, X. Bao, Gary GrÃ©wal, Dilip K. Banerji, Peng Du. isca, 16(1):13-33, 2009.

Near-linear wirelength estimation for FPGA placementMing Xu, Gary GrÃ©wal, Shawki Areibi, Charlie Obimbo, Dilip K. Banerji. ccece 2009: 1198-1203 [doi]

2006

Clustering Hanan Points to Reduce Vlsi Interconnect Routing TimesShouvik Chowdhury, Gary William Grewal, Dilip K. Banerji. ccece 2006: 1223-1227 [doi]

Optimized Memory Assignment for DSPsGary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton, Mario Ventresca. cec 2006: 64-72 [doi]

2004

A Fast Hierarchical Approach to FPGA PlacementPeng Du, Gary William Grewal, Shawki Areibi, Dilip K. Banerji. csreaESA 2004: 497-503

Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner TreesGary William Grewal, Thomas Charles Wilson, Ming Xu, Dilip K. Banerji. vlsid 2004: 855-862 [doi]

2003

Routability Prediction for Field Programmable Gate Arrays with a Routing HierarchyZhibin Dai, Dilip K. Banerji. vlsid 2003: 85-90 [doi]

1999

Routability Prediction for Hierarchical FPGAsWei Li, Dilip K. Banerji. glvlsi 1999: 256-259 [doi]

1996

A Modified Approach to Test Plan Generation for Combinational Logic BlocksAnupam Basu, Dilip K. Banerji, Amit Basu, Thomas Charles Wilson, Jayanti C. Majithia. vlsi, 4(3):243-256, 1996. [doi]

Instruction-Set Matching and GA-based Selection for Embedded-Processor Code GenerationJ. Shu, Thomas Charles Wilson, Dilip K. Banerji. vlsid 1996: 73-76 [doi]

1995

An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath SynthesisThomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji. vlsi, 3(1):21-36, 1995. [doi]

1994

An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block SynthesisThomas Charles Wilson, Gary William Grewal, Dilip K. Banerji. iccd 1994: 581-586

An ILP-based approach to code generationThomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji. Dagstuhl 1995: 103-118

An integrated approach to retargetable code generationThomas Charles Wilson, Gary Gréwal, Ben Halley, Dilip K. Banerji. isss 1994: 70-75 [doi]

1993

An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath SynthesisThomas Charles Wilson, Nilanjan Mukherjee, M. K. Garg, Dilip K. Banerji. vlsid 1993: 192-197

MinMux: a new approach for global minimization of multiplexers in interconnect synthesisThomas Charles Wilson, M. K. Garg, R. Deadman, Ben Halley, Dilip K. Banerji. glvlsi 1993: 132-138 [doi]

1992

An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-TestAnupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia. vlsid 1992: 354-355 [doi]

1991

Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuitsAnupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia. glvlsi 1991: 340-341 [doi]

Test plan generation and concurrent scheduling of tests in the presence of conflictsThomas Charles Wilson, Anupam Basu, Dilip K. Banerji, Jayanti C. Majithia. glvlsi 1991: 243-248 [doi]

1988

1983

Representation and processing of fractions in a residue systemDilip K. Banerji, Saroj Kaushik. arith 1983: 29-36 [doi]

1976

Using a Microprocessor in an Intelligent Graphics TerminalJacques Raymond, Dilip K. Banerji. Computer, 9(4):18-25, 1976. [doi]

1975

A cross-assembler and simulator for the "SKINNY" microcomputerDilip K. Banerji, Jacques Raymond. jsa, 1(5):25-29, 1975. [doi]

1974

A Novel Implementation Method for Addition and Subtraction in Residue Number SystemsDilip K. Banerji. TC, 23(1):106-109, 1974. [doi]

1973

On Control Memory Minimization in Microprogrammed Digital ComputersS. R. Das, Dilip K. Banerji, A. Chattopadhyay. TC, 22(9):845-848, 1973. [doi]

1972

On Translation Algorithms in Residue Number SystemsDilip K. Banerji, Janusz A. Brzozowski. TC, 21(12):1281-1285, 1972. [doi]

1969

Sign Detection in Residue Number SystemsDilip K. Banerji, Janusz A. Brzozowski. TC, 18(4):313-320, 1969. [doi]

Sign in or sign up to see more results.

runs on WebDSL