Dmitrij Kissler - researchr alias

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Viewing Publication 1 - 16 from 16

2012

Power-Efficient Tightly-Coupled Processor Arrays for Digital Signal ProcessingDmitrij Kissler. PhD thesis, University of Erlangen-Nuremberg, 2012. [doi]

2011

Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor ArraysDmitrij Kissler, Frank Hannig, Jürgen Teich. jolpe, 7(1):29-40, 2011. [doi]

Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor ArraysDmitrij Kissler, D. Gran, Zoran Salcic, Frank Hannig, Jürgen Teich. esl, 3(2):58-61, 2011. [doi]

2009

A holistic approach for tightly coupled reconfigurable parallel processorsHritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, JÃ¼rgen Teich, Bernard Pottier. mam, 33(1):53-62, 2009. [doi]

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable ArchitecturesDmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich. jolpe, 5(1):96-105, 2009. [doi]

2008

2007

Massively Parallel Processor Architectures: A Co-design ApproachHritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier. recosoc 2007: 61-68

Efficient event-driven simulation of parallel processor architecturesAlexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich. scopes 2007: 71-80 [doi]

Modeling of Interconnection Networks in Massively Parallel Processor ArchitecturesAlexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement. arcs 2007: 268-282 [doi]

A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative EvaluationJürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet. ersa 2007: 14-24

2006

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