Gustavo A. Ruiz - researchr alias

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Viewing Publication 1 - 13 from 13

2014

Efficient low-power register array with transposed access modeGustavo A. Ruiz, Mercedes Granda. mj, 45(4):463-467, 2014. [doi]

2013

A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVCMiguel A. Manzano, Juan A. Michell, Gustavo A. Ruiz. vlsisp, 70(1):59-73, 2013. [doi]

2011

A high-throughput ASIC processor for 8×8 transform coding in H.264/AVCJuan A. Michell, José M. Solana, Gustavo A. Ruiz. spic, 26(2):93-104, 2011. [doi]

Efficient canonic signed digit recodingGustavo A. Ruiz, Mercedes Granda. mj, 42(9):1090-1097, 2011. [doi]

An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTVGustavo A. Ruiz, Juan A. Michell. vlsisp, 62(3):443-457, 2011. [doi]

An efficient VLSI processor chip for variable block size integer motion estimation in H.264/AVCGustavo A. Ruiz, Juan A. Michell. spic, 26(6):289-303, 2011. [doi]

2008

Efficient implementation of 3X for radix-8 encodingGustavo A. Ruiz, Mercedes Granda. mj, 39(1):152-159, 2008. [doi]

2006

High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor ChipGustavo A. Ruiz, Juan A. Michell, Angel M. Buron. vlsisp, 45(3):161-175, 2006. [doi]

2005

Parallel-pipeline 8×8 forward 2-D ICT processor chip for image codingGustavo A. Ruiz, Juan A. Michell, Angel M. Buron. tsp, 53(2-1):714-723, 2005. [doi]

High throughput 2D DCT/IDCT processor for video codingGustavo A. Ruiz, Juan A. Michell, Angel M. Buron. icip 2005: 1036-1039 [doi]

2003

Parallel-pipelined architecture for 2-D ICT VLSI implementationJuan A. Michell, Gustavo A. Ruiz, Angel M. Buron. icip 2003: 89-92

1998

Memory efficient programmable processor chip for inverse Haar transformGustavo A. Ruiz, Juan A. Michell. tsp, 46(1):263-268, 1998. [doi]

Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuitsGustavo A. Ruiz. jssc, 33(4):604-613, 1998. [doi]

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