H. J. Liao - researchr alias

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Viewing Publication 1 - 4 from 4

2018

A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET TechnologyMahmut E. Sinangil, Yen-Ting Lin, H. J. Liao, Jonathan Chang. vlsic 2018: 13-14 [doi]

2017

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applicationsMichael Clinton, Hank Cheng, H. J. Liao, Robin Lee, Ching-Wei Wu, Johnny Yang, Hau-Tai Hsieh, Frank Wu, Jung-Ping Yang, Atul Katoch, Arun Achyuthan, Donald Mikan, Bryan Sheffield, Jonathan Chang. isscc 2017: 210-211 [doi]

2007

A 45nm dual-port SRAM with write and read capability enhancement at low voltageD. P. Wang, H. J. Liao, H. Yamauchi, Y. H. Chen, Y.-L. Lin, S.-H. Lin, D. C. Liu, H.-C. Chang, W. Hwang. socc 2007: 211-214 [doi]

1993

A BiCMOS dynamic carry lookahead adder circuit for VLSI implementation of high-speed arithmetic unitJames B. Kuo, H. J. Liao, H. P. Chen. jssc, 28(3):375-378, March 1993. [doi]

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