Hanpei Koike - researchr alias

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Viewing Publication 1 - 45 from 45

2023

A Cryogenic CMOS Current Integrator and Correlation Double Sampling Circuit for Spin Qubit ReadoutHiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori. tcasI, 70(12):5220-5228, December 2023. [doi]

2022

A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current ResolutionHiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori. vlsit 2022: 234-235 [doi]

2020

Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shippingYasuhiro Ogasahara, Yohei Hori, Toshihiro Katashita, Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda, Hanpei Koike. integration, 71:144-153, 2020. [doi]

2018

Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA DeviceToshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike. ieicet, 101-D(2):303-313, 2018. [doi]

2016

Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS TechnologyMasakazu Hioki, Hanpei Koike. ieicet, 99-D(12):3082-3089, 2016. [doi]

Implementation of pseudo linear feedback shift register physical unclonable function on siliconYasuhiro Ogasahara, Yohei Hori, Hanpei Koike. iscas 2016: 758-761 [doi]

2015

Standard cell implementation of buskeeper PUF with symmetric inverters and neighboring cells for passing randomness testsYasuhiro Ogasahara, Yohei Hori, Hanpei Koike. gcce 2015: 550-551 [doi]

th control, low process variability, and steep SS with low on-current of new structure transistors to ultra-low voltage designsYasuhiro Ogasahara, Tadashi Nakagawa, Toshihiro Sekigawa, Toshiyuki Tsutsumi, Hanpei Koike. ieiceee, 12(15):20150460, 2015. [doi]

2013

Fully-functional FPGA prototype with fine-grain programmable body biasingMasakazu Hioki, Toshihiro Sekigawa, Tadashi Nakagawa, Hanpei Koike, Yohei Matsumoto, Takashi Kawanami, Toshiyuki Tsutsumi. fpga 2013: 73-80 [doi]

2012

2010

2009

High-speed low-power FinFET based domino logicSeid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee. aspdac 2009: 829-834 [doi]

2008

2007

A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA ChipMasakazu Hioki, Takashi Kawanami, Yohei Matsumoto, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Toshiyuki Tsutsumi. fpt 2007: 285-288 [doi]

Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGATakashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike. ieicet, 90-D(12):1947-1955, 2007. [doi]

Performance and yield enhancement of FPGAs with within-die variation using multiple configurationsYohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike. fpga 2007: 169-177 [doi]

Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based TechnologyShin-ichi O'Uchi, Meishoku Masahara, Kunihiro Sakamoto, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki. cicc 2007: 33-36 [doi]

2006

2005

XDXMOS: a novel technique for the double-gate MOSFETs logic circuits - to achieve high drive current and small input capacitance togetherHanpei Koike, Toshihiro Sekigawa. cicc 2005: 247-250 [doi]

2004

1998

Fast Speculative Search Engine on the Highly Parallel Computer EM-XHayato Yamana, Hanpei Koike, Yuetsu Kodama, Hirofumi Sakane, Yoshinori Yamaguchi. sigir 1998: 390 [doi]

1997

Parallel Execution of Radix Sort Program Using Fine-Grain CommunicationYuetsu Kodama, Hirofumi Sakane, Hanpei Koike, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi. IEEEpact 1997: 136-145 [doi]

1994

Architecture of parallel management kernel for PIE64Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka. fgcs, 10(1):29-43, 1994. [doi]

A Performance Debugger for a Parallel Logic Programming Language FlengJun ichi Tatemura, Hanpei Koike, Hidehiko Tanaka. tppp 1995: 284-299

A Fleng Compiler for PIE64Hidemoto Nakada, Takuya Araki, Hanpei Koike, Hidehiko Tanaka. ifipPACT 1994: 257-266

1993

1992

Architecture of Parallel Management Kernel for PIE64Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka. parle 1992: 685-700

HyperDEBU: A Multiwindow Debugger for Parallel Logic ProgramsJun ichi Tatemura, Hanpei Koike, Hidehiko Tanaka. pepc 1992: 87-105

UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka. fgcs 1992: 715-722

1991

A Static Load Partitioning Method based on Execution Profile for Committed Choice LanguagesYasuo Hidaka, Hanpei Koike, Jun ichi Tatemura, Hidehiko Tanaka. SLP 1991: 470-484

1989

Distributed Garbage Collection for the Parallel Inference Engine PIE64Lu Xu, Hanpei Koike, Hidehiko Tanaka. SLP 1989: 922-941

Distributed Garbage Collection for the Parallel Inference Machine PIE64Lu Xu, Hanpei Koike, Hidehiko Tanaka. ifip 1989: 1161-1166

1988

Multi-Context Processing and Data Balancing Mechanism of the Parallel Inference Machine PIE64Hanpei Koike, Hidehiko Tanaka. fgcs 1988: 970-977

1986

Fast Execution Mechanisms of Parallel Inference Engine PIE: PIEpelined Goal Rewriting and Goal MulticastingHanpei Koike, Hidehiko Tanaka. lp 1987: 159-169

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