Heinrich Klar - researchr alias

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Viewing Publication 1 - 19 from 19

2016

Implementation and design investigation of 40 Gbps driver IC for silicon photonics ring-modulator in SiGe 130-nmAdel Fatemi, Heinrich Klar, Friedel Gerfers. iscas 2016: 2387-2390 [doi]

2005

A cascade 3-1-1 multibit /spl Sigma//spl Delta/ A/D modulator with reduced sensitivity to non-idealitiesYi Yin, Heinrich Klar, Peter Wennekers. iscas 2005: 3087-3090 [doi]

2004

A novel broadband cascade sigma-delta analog-to-digital converterYi Yin, Heinrich Klar, Peter Wennekers. iastedCCS 2004: 471-476

2003

Image preprocessing with dynamic synapsesN. Mehrtash, D. Jung, Heinrich Klar. nca, 12(1):33-41, 2003. [doi]

2INN): a system approachNasser Mehrtash, Dietmar Jung, Heik Heinrich Hellmich, Tim Schönauer, Vi Thanh Lu, Heinrich Klar. tnn, 14(5):980-992, 2003. [doi]

2002

Simulation of spiking neural networks -- architectures and implementationsMartin Schäfer, Tim Schönauer, Carsten Wolff, Georg Hartmann, Heinrich Klar, Ulrich Rückert. ijon, 48(1-4):647-679, 2002. [doi]

NeuroPipe-Chip: A digital neuro-processor for spiking neural networksTim Schönauer, Sahin Atasoy, Nasser Mehrtash, Heinrich Klar. tnn, 13(1):205-213, 2002. [doi]

2000

Simulation of a Digital Neuro-Chip for Spiking Neural NetworksTim Schönauer, S. Atasoy, N. Mehrtash, Heinrich Klar. ijcnn 2000: 490-498 [doi]

1998

A 12-bit medium-time analog storage device in a CMOS standard processMartin Ehlert, Heinrich Klar. jssc, 33(7):1139-1143, 1998. [doi]

1997

1995

Calculation of the soft error rate of submicron CMOS logic circuitsT. Juhnke, Heinrich Klar. jssc, 30(7):830-834, July 1995. [doi]

Hardware Requirements for Spike-Processing Neural NetworksUlrich Roth, Axel Jahnke, Heinrich Klar. iwann 1995: 720-727

General algorithms for a simplified addition of 2's complement numbersO. Salomon, Jorg-Michael Green, Heinrich Klar. jssc, 30(7):839-844, July 1995. [doi]

1993

Design of a general-purpose neural signal processorJörg Beichter, Nico Brüls, Elisabeth Sicheneder, Ulrich Ramacher, Heinrich Klar. ijon, 5(1):17-23, 1993.

Self-Timed Fully Pipelined MultipliersO. Salomon, Heinrich Klar. ifip10-5 1993: 45-55

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