Hendrik Seidel - researchr alias

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Viewing Publication 1 - 11 from 11

2006

A GFLOPS Vector-DSP for Broadband Wireless ApplicationsE. Matu, Hendrik Seidel, Torsten Limberg, Pablo Robelly, Gerhard Fettweis. cicc 2006: 543-546 [doi]

Energy efficiency vs. programmability trade-off: architectures and design principlesPablo Robelly, Hendrik Seidel, K.-C. Chen, Gerhard Fettweis. date 2006: 587-592 [doi]

A task level programmable processorHendrik Seidel. PhD thesis, Dresden University of Technology, 2006.

2005

A Compiler-friendly and Low-power DSP architectureEmil Matús, Gordon Cichon, Hendrik Seidel, Pablo Robelly, Torsten Limberg, Gerhard Fettweis. gi 2005: 459

Design and automatic code generation of the LMS algorithm for SIMD signal processorsJuan Pablo Robelly, Gordon Cichon, Hendrik Seidel, Gerhard Fettweis. icassp 2005: 81-84 [doi]

2004

Compiler Scheduling for STA-ProcessorsGordon Cichon, Pablo Robelly, Hendrik Seidel, Marcus Bronzel, Gerhard Fettweis. parelec 2004: 45-50 [doi]

Synchronous Transfer Architecture (STA)Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matús, Marcus Bronzel, Gerhard Fettweis. samos 2004: 343-352 [doi]

Automatic Code Generation for SIMD DSP Architectures: An Algebraic ApproachPablo Robelly, Gordon Cichon, Hendrik Seidel, Gerhard Fettweis. parelec 2004: 372-375 [doi]

Implementation of recursive digital filters into vector SIMD DSP architecturesJuan Pablo Robelly, Gordon Cichon, Hendrik Seidel, Gerhard Fettweis. icassp 2004: 165-168 [doi]

Hardware / Software Co-Design of a SIMD-DSP-Based DVB-T ReceiverHendrik Seidel, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard Fettweis. parelec 2004: 221-225 [doi]

Generated DSP Cores for Implementation of an OFDM Communication SystemHendrik Seidel, Emil Matús, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard Fettweis. samos 2004: 353-362 [doi]

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