Hironori Banba - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 5 from 5

2001

Wordline voltage generating system for low-power low-voltage flash memoriesToru Tanzawa, Akira Umezawa, Masao Kuriyama, Tadayuki Taura, Hironori Banba, Takeshi Miyaba, Hitoshi Shiga, Yoshinori Takano, Shigeru Atsumi. jssc, 36(1):55-63, 2001. [doi]

2000

Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data busToshimasa Namekawa, Shinji Miyano, Ryo Fukuda, Ryo Haga, Osamu Wada, Hironori Banba, Satoru Takeda, Kazuhiro Suda, Kenichiro Mimoto, Satoshi Yamaguchi, Tsutomu Ohkubo, Hiroshi Takato, Kenji Numata. jssc, 35(5):705-712, 2000. [doi]

1999

A CMOS bandgap reference circuit with sub-1-V operationHironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa, Shigeru Atsumi, Koji Sakui. jssc, 34(5):670-674, 1999. [doi]

1994

A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operationShigeru Atsumi, Masao Kuriyama, Akira Umezawa, Hironori Banba, Kiyomi Naruke, Seiji Yamada, Yoichi Ohshima, Masamitsu Oshikiri, Yohei Hiura, Tomoko Yamane, Kuniyoshi Yoshikawa. jssc, 29(4):461-469, April 1994. [doi]

1992

A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structureAkira Umezawa, Shigeru Atsumi, Masao Kuriyama, Hironori Banba, Ken-ichi Imamiya, Kiyomi Naruke, Seiji Yamada, Etsushi Obi, Masamitsu Oshikiri, Tomoko Suzuki, Sumio Tanaka. jssc, 27(11):1540-1546, November 1992. [doi]

Sign in or sign up to see more results.

runs on WebDSL