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Viewing Publication 1 - 28 from 28

2023

SEE sensitivity of a COTS 28-nm SRAM-based FPGA under thermal neutrons and different incident anglesJuan Carlos Fabero, Golnaz Korkian, Francisco J. Franco, Guillaume Hubert, Hortensia Mecha, Manon Letiche, Juan Antonio Clemente. mam, 96:104743, February 2023. [doi]

2022

Single Event Upsets Under Proton, Thermal, and Fast Neutron Irradiation in Emerging Nonvolatile MemoriesGolnaz Korkian, Daniel León, Francisco J. Franco, Juan Carlos Fabero, Manon Letiche, Yolanda Morilla, Pedro Martin-Holgado, Helmut Puchner, Hortensia Mecha, Juan Antonio Clemente. access, 10:114566-114585, 2022. [doi]

2021

Thermal Neutron-induced SEUs on a COTS 28-nm SRAM-based FPGA under Different Incident AnglesJuan Carlos Fabero, Golnaz Korkian, Francisco J. Franco, Hortensia Mecha, Manon Letiche, Juan Antonio Clemente. latw 2021: 1-6 [doi]

2020

Analysis of a Pipelined Architecture for Sparse DNNs on Embedded SystemsAdrián Alcolea Moreno, Javier Olivito, Javier Resano, Hortensia Mecha. tvlsi, 28(9):1993-2003, 2020. [doi]

2018

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate arrayJavier Olivito, Felipe Serrano, Juan Antonio Clemente, Hortensia Mecha, Javier Resano. iet-cdt, 12(4):150-157, 2018. [doi]

2016

Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAsJuan Antonio Clemente, Wassim Mansour, Rafic Ayoubi, Felipe Serrano, Hortensia Mecha, Haissam Ziade, Wassim El Falou, Raoul Velazco. ijon, 171:1606-1609, 2016. [doi]

Radiation-hardened DSP configurations for implementing arithmetic functions on FPGAMarcos Sanchez-Elez, Inmaculada Pardines, Felipe Serrano, Hortensia Mecha. date 2016: 1501-1504 [doi]

2010

A Constant Complexity Allocation Algorithm for Reconfigurable Systems Management Adapted to Heterogeneous Workload ProfilesSara Román Navarro, Hortensia Mecha, Daniel Mozos. ersa 2010: 259-262

2009

3D FPGA resource management and fragmentation metric for hardware multitaskingJose Antonio Valero, Julio SeptiÃ©n, Daniel Mozos, Hortensia Mecha. ipps 2009: 1-7 [doi]

2008

Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw systemAngel Luis González Bravo, Hortensia Mecha, Julio Septién, Sara Román Navarro, Daniel Mozos. ersa 2008: 307-308

Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arraysS. Roman, Hortensia Mecha, Daniel Mozos, Julio Septién. iet-cdt, 2(6):401-412, 2008. [doi]

FPGA Resource Management Using Internal RAM as Aata CacheLaura Sanchez, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo. ersa 2008: 317-318

Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitaskingJulio Septién, Daniel Mozos, Hortensia Mecha, Jesús Tabero, Miguel Angel García de Dios. ipps 2008: 1-8 [doi]

Allocation heuristics and defragmentation measures for reconfigurable systems managementJesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos. integration, 41(2):281-296, 2008. [doi]

Resource Management for Hw Multitasking in Three Dimensional FPGAsJose Antonio Valero, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo. ersa 2008: 319-320

2006

2004

A Low Fragmentation Heuristic for Task Placement in 2D RTR HW ManagementJesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos. fpl 2004: 241-250 [doi]

2003

A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance RequirementsJavier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién. patmos 2003: 580-589 [doi]

Analyzing communication overheads during hardware/software partitioningJavier Resano, M. Elena Pérez, Daniel Mozos, Hortensia Mecha, Julio Septién. mj, 34(11):1001-1007, 2003. [doi]

1999

Unified data path allocation and BIST intrusionKatzalin Olcoz, Francisco Tirado, Hortensia Mecha. integration, 28(1):55-99, 1999. [doi]

1998

A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning ProcessJ. A. Maestro, Daniel Mozos, Hortensia Mecha. date 1998: 218-225 [doi]

1997

Interconnection Delay and Clock Cycle Selection in High Level SynthesisHortensia Mecha, Milagros Fernández. vlsid 1997: 504-505 [doi]

A unified approach for scheduling and allocationR. Moreno, Román Hermida, Milagros Fernández, Hortensia Mecha. integration, 23(1):1-35, 1997. [doi]

1996

A method for area estimation of data-path in high level synthesisHortensia Mecha, Milagros Fernández, Francisco Tirado, Julio Septién, D. Motes, Katzalin Olcoz. tcad, 15(2):258-265, 1996. [doi]

1994

Clock cycle estimation based on dead time and control unit area minimizationHortensia Mecha, Milagros FernÃ¡ndez, RomÃ¡n Hermida, Daniel Mozos, Katzalin Olcoz. jsa, 40(10-12):821-824, 1994. [doi]

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