Hyun J. Shin - researchr alias

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Viewing Publication 1 - 6 from 6

2004

A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial linkYongsam Moon, Young Soo Park, Namhoon Kim, Gijung Ahn, Hyun J. Shin, Deog Kyoon Jeong. jssc, 39(5):795-803, 2004. [doi]

1999

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interfaceYasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada. jssc, 34(4):494-501, 1999. [doi]

1996

Single-chip 4×500-MBd CMOS transceiverAlbert X. Widmer, Kevin R. Wrenner, Herschel A. Ainspan, Ben Parker, Pierre Austruy, Bernard Brezzo, Anne-Marie Haen, John F. Ewen, Mehmet Soyuer, Alain Blanc, Jean-Claude Abbiate, Alina Deutsch, Hyun J. Shin. jssc, 31(12):2004-2014, 1996. [doi]

1995

Digital FIR filters for high speed PRML disk read channelsDale J. Pearson, Scott K. Reynolds, Andrew C. Megdanis, Sudhir M. Gowda, Kevin R. Wrenner, Michael Immediato, Richard L. Galbraith, Hyun J. Shin. jssc, 30(12):1517-1523, December 1995. [doi]

Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applicationsHyun J. Shin, Dale J. Pearson, Scott K. Reynolds, Andrew C. Megdanis, Sudhir M. Gowda, Kevin R. Wrenner. ibmrd, 39(1-2):83-92, 1995.

1994

A self-biased feedback-controlled pull-down emitter follower for high-speed low-power bipolar logic circuitsHyun J. Shin. jssc, 29(4):523-528, April 1994. [doi]

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