Igor Lemberski - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 16 from 16

2021

Resubstitution method for big size Boolean logic design targeting look-up-table implementationIgor Lemberski, Artjoms Suponenkovs. ijcta, 49(8):2411-2424, 2021. [doi]

2019

LUT-Oriented Asynchronous Logic Design Based on ResubstitutionIgor Lemberski, Artjoms Suponenkovs, Marina Uhanova. dtis 2019: 1-4 [doi]

2018

Asynchronous logiс one-level LUT design based on partial acknowledgementIgor Lemberski, Artjoms Suponenkovs. mj, 80:53-61, 2018. [doi]

Asynchronous logic design targeting LUTsIgor Lemberski, Artjoms Suponenkovs. meco 2018: 1-6 [doi]

2017

Asynchronous Logic Implementation Based on Factorized DIMSIgor Lemberski. jcsc, 26(5):1-9, 2017. [doi]

2015

Literal Decomposition for LUT-Oriented Asynchronous Dual-Rail Logic SynthesisIgor Lemberski. jcsc, 24(7), 2015. [doi]

2014

Dual-rail asynchronous logic multi-level implementationIgor Lemberski, Petr Fiser. integration, 47(1):148-159, 2014. [doi]

Asynchronous sum-of-products logic minimization and orthogonalizationIgor Lemberski, Petr Fiser, Ruslan Suleimanov. ijcta, 42(6):562-571, 2014. [doi]

2010

Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong ConstraintsIgor Lemberski, Petr Fiser. dsd 2010: 155-162 [doi]

2009

Asynchronous two-level logic of reduced costIgor Lemberski, Petr Fiser. ddecs 2009: 68-73 [doi]

2007

Avoiding Hazards for Speed-Independent Logic DesignIgor Lemberski. wce 2007: 274-278

Cost Effective Implementation of Asynchronous Two-Level LogicIgor Lemberski. wce 2007: 159-164

2002

Optimal Two-Level Delay - Insensitive Implementation of Logic FunctionsIgor Lemberski, Mark B. Josephs. patmos 2002: 92-100 [doi]

1999

Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAsIgor Lemberski. glvlsi 1999: 242-243 [doi]

1998

Modified Approach to Automata State Encoding for LUT FPGA ImplementationIgor Lemberski. euromicro 1998: 10196-10199 [doi]

XILINX4000 Architecture-Driven Synthesis for SpeedIgor Lemberski, M. Ratniece. fpl 1998: 476-480 [doi]

Sign in or sign up to see more results.

runs on WebDSL