JÃ¼rgen Teich - researchr alias

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Viewing Publication 1 - 20 from 20

2009

A holistic approach for tightly coupled reconfigurable parallel processorsHritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, JÃ¼rgen Teich, Bernard Pottier. mam, 33(1):53-62, 2009. [doi]

Impact of Loop Tiling on the Controller Logic of Acceleration EnginesHritam Dutta, Jiali Zhai, Frank Hannig, JÃ¼rgen Teich. asap 2009: 161-168 [doi]

Electronic System-Level Synthesis MethodologiesAndreas Gerstlauer, Christian Haubelt, Andy D. Pimentel, Todor Stefanov, Daniel D. Gajski, JÃ¼rgen Teich. tcad, 28(10):1517-1530, 2009. [doi]

Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysisMichael GlaÃŸ, Martin Lukasiewycz, JÃ¼rgen Teich, Unmesh D. Bordoloi, Samarjit Chakraborty. dac 2009: 43-46 [doi]

Incorporating graceful degradation into embedded system designMichael GlaÃŸ, Martin Lukasiewycz, Christian Haubelt, JÃ¼rgen Teich. date 2009: 320-323 [doi]

Model-based synthesis and optimization of static multi-rate image processing algorithmsJoachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, JÃ¼rgen Teich. date 2009: 135-140 [doi]

Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble SystemsDirk Koch, Christian Beckhoff, JÃ¼rgen Teich. fccm 2009: 251-254 [doi]

System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their PerformanceVahid Lari, Frank Hannig, JÃ¼rgen Teich. icppw 2009: 528-534 [doi]

Exploiting data-redundancy in reliability-aware networked embedded system designMartin Lukasiewycz, Michael GlaÃŸ, JÃ¼rgen Teich. codes 2009: 229-238 [doi]

FlexRay schedule optimization of the static segmentMartin Lukasiewycz, Michael GlaÃŸ, JÃ¼rgen Teich, Paul Milbredt. codes 2009: 363-372 [doi]

Combined system synthesis and communication architecture exploration for MPSoCsMartin Lukasiewycz, Martin StreubÃ¼hr, Michael GlaÃŸ, Christian Haubelt, JÃ¼rgen Teich. date 2009: 472-477 [doi]

Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics ProcessorsRichard Membarth, Frank Hannig, Hritam Dutta, JÃ¼rgen Teich. samos 2009: 277-288 [doi]

Acceleration of Multiresolution Imaging Algorithms: A Comparative StudyRichard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, JÃ¼rgen Teich. asap 2009: 211-214 [doi]

Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA AcceleratorsJoon Edward Sim, Weng-Fai Wong, JÃ¼rgen Teich. fccm 2009: 279-282 [doi]

Self-organizing Bandwidth Sharing in Priority-Based Medium AccessStefan Wildermann, Tobias Ziermann, JÃ¼rgen Teich. saso 2009: 144-153 [doi]

CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data ratesTobias Ziermann, Stefan Wildermann, JÃ¼rgen Teich. date 2009: 1088-1093 [doi]

2008

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