Jean-Louis Houle - researchr alias

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Viewing Publication 1 - 11 from 11

2005

A system level implementation strategy and partitioning heuristic for LUT-based applicationsHakim Khali, Yvon Savaria, Jean-Louis Houle. cee, 31(7):485-502, 2005. [doi]

2003

Improvement of sensor accuracy in the case of a variable surface reflectance gradient for active laser range findersHakim Khali, Yvon Savaria, Jean-Louis Houle, Marc Rioux, J.-Angelo Beraldin, D. Poussart. tim, 52(6):1799-1808, 2003. [doi]

2000

A VLSI architecture of 2D wavelet transformsChokri Achour, Jean-Louis Houle, Jacob Davidson. icecsys 2000: 370-373 [doi]

1995

Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated CircuitsClaude Thibeault, Yvon Savaria, Jean-Louis Houle. TC, 44(5):724-728, 1995.

1994

FPGA Implementation of Wavelet TransformsChokri Achour, Jacob Davidson, Jean-Louis Houle. appinf 1994: 241-244

A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated CircuitsClaude Thibeault, Yvon Savaria, Jean-Louis Houle. TC, 43(6):687-698, 1994.

1993

A High Speed Parallel Structure for the Basic Wavelet Transform AlgorithmHakim Khali, Jean-Louis Houle, Yvon Savaria. iscas 1993: 1971-1974

1992

Performance improvements to VLSI parallel systems, using dynamic concatenation of processing resourcesDaniel Audet, Yvon Savaria, Jean-Louis Houle. pc, 18(2):149-167, 1992.

Heuristic Prediction of the Optimum Number of spares in Defect-Tolerant Integrated CircuitsClaude Thibeault, Yvon Savaria, Jean-Louis Houle. jcsc, 2(2):81-100, 1992. [doi]

Test quality of hierarchical defect-tolerant integrated circuitsClaude Thibeault, Yvon Savaria, Jean-Louis Houle. et, 3(1):93-102, 1992. [doi]

1990

Impact of reconfiguration logic on the optimization of defect-tolerant integrated circuitsClaude Thibeault, Jean-Louis Houle. ftcs 1990: 158-165 [doi]

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