Jeffrey B. Goeders - researchr alias

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Viewing Publication 1 - 8 from 8

2016

LegUp High-Level SynthesisAndrew Canis, Jongsok Choi, Blair Fort, Bain Syrowik, Ruolong Lian, Yu-Ting Chen, Hsuan Hsiao, Jeffrey B. Goeders, Stephen Dean Brown, Jason Helge Anderson. In Dirk Koch, Frank Hannig, Daniel Ziener, editors, FPGAs for Software Programmers. pages 175-190, Springer, 2016. [doi]

Systems-on-Chip on FPGAsJeffrey B. Goeders, Graham M. Holland, Lesley Shannon, Steven J. E. Wilton. In Dirk Koch, Frank Hannig, Daniel Ziener, editors, FPGAs for Software Programmers. pages 261-283, Springer, 2016. [doi]

2015

Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAsJeffrey B. Goeders, Steven J. E. Wilton. fccm 2015: 127-134 [doi]

2014

Power Aware Architecture Exploration for Field Programmable Gate ArraysJeffrey B. Goeders, Steven J. E. Wilton. jolpe, 10(3):297-312, 2014. [doi]

Effective FPGA debug for high-level synthesis generated circuitsJeffrey B. Goeders, Steven J. E. Wilton. fpl 2014: 1-8 [doi]

Faster FPGA Debug: Efficiently Coupling Trace Instruments with User CircuitryEddie Hung, Jeffrey B. Goeders, Steven J. E. Wilton. arc 2014: 73-84 [doi]

2012

VersaPower: Power estimation for diverse FPGA architecturesJeffrey B. Goeders, Steven J. E. Wilton. fpt 2012: 229-234 [doi]

2011

Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window DecompositionJeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton. reconfig 2011: 41-48 [doi]

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