John Moondanos - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 16 from 16

2018

A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engineMichael K. Tsiampas, Nestor E. Evmorfopoulos, Konstantis Daloukas, John Moondanos, Georgios I. Stamoulis. dtis 2018: 1-6 [doi]

2010

Characterization of the worst-case current waveform excitations in general RLC-model power grid analysisNestoras E. Evmorfopoulos, Maria-Aikaterini Rammou, George Stamoulis, John Moondanos. iccad 2010: 824-830 [doi]

2007

From Error to Error: Logic Debugging in the Many-Core EraJohn Moondanos. ENTCS, 174(4):3-7, 2007. [doi]

An Efficient Diagnostic Test Pattern Generation Framework Using Boolean SatisfiabilityFeijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, Ziyad Hanna. ats 2007: 288-294 [doi]

2006

Generation of shorter sequences for high resolution error diagnosis using sequential SATSung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna. aspdac 2006: 25-29 [doi]

2005

JPEG Encoding on the Intel MXP5800: A Platform-Based Design Case StudyAbhijit Davare, Qi Zhu, John Moondanos, Alberto L. Sangiovanni-Vincentelli. estimedia 2005: 89-94 [doi]

2004

A Signal Correlation Guided Circuit-SAT SolverFeng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna. jucs, 10(12):1629-1654, 2004. [doi]

Preserving synchronizing sequences of sequential circuits after retimingMaher N. Mneimneh, Karem A. Sakallah, John Moondanos. aspdac 2004: 579-584 [doi]

2003

A signal correlation guided ATPG solver and its applications for solving difficult industrial casesFeng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna. dac 2003: 436-441 [doi]

2002

TRANS: efficient sequential verification of loop-free circuitsZurab Khasidashvili, John Moondanos, Ziyad Hanna. hldvt 2002: 115-120 [doi]

2001

An enhanced cut-points algorithm in formal equivalence verificationZurab Khasidashvili, John Moondanos, Daher Kaiss, Ziyad Hanna. hldvt 2001: 171-176 [doi]

CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative EliminationJohn Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss. cav 2001: 131-143 [doi]

1997

Automatic verification of implementations of large circuits against HDL specificationsYatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos. tcad, 16(3):217-228, 1997. [doi]

1994

Verification of Circuits Described in VHDL through Extraction of Design IntentYatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell. vlsid 1994: 417-420

Abstraction of data path registers for multilevel verification of large circuitsYatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell. glvlsi 1994: 11-14 [doi]

1992

Sequential Redundancy Identification Using Verification TechniquesJohn Moondanos, Jacob A. Abraham. itc 1992: 197-205

Sign in or sign up to see more results.

runs on WebDSL