Junichi Miyakoshi - researchr alias

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Viewing Publication 1 - 23 from 23

2023

Social Co-OS: Cyber-human social Co-operating systemTakeshi Kato, Yasuyuki Kudo, Junichi Miyakoshi, Misa Owa, Yasuhiro Asa, Takashi Numata, Ryuji Mine, Hiroyuki Mizuno. iet-cps, 8(1):1-14, March 2023. [doi]

2013

False-positive reduction of liver tumor detection using ensemble learning methodAtsushi Miyamoto, Junichi Miyakoshi, Kazuki Matsuzaki, Toshiyuki Irie. miip 2013: [doi]

2012

Metastatic liver tumor detection from 3D CT images using a level set algorithm with liver-edge termJunichi Miyakoshi, Shuntaro Yui, Kazuki Matsuzaki, Toshiyuki Irie. miip 2012: [doi]

Size-adaptive hepatocellular carcinoma detection from 3D CT images based on the level set methodShuntaro Yui, Junichi Miyakoshi, Kazuki Matsuzaki, Toshiyuki Irie, Ryo Kurazume. micad 2012: [doi]

2011

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose CoreOsamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima. ieicet, 94-C(4):663-669, 2011. [doi]

2010

2008

Novel Video Memory Reduces 45 of Bitline Power Using Majority Logic and Data-Bit ReorderingHidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto. tvlsi, 16(6):620-627, 2008. [doi]

An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encodingKosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto. icecsys 2008: 1179-1182 [doi]

A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encodingYuichiro Murachi, Kusuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto. iscas 2008: 848-851 [doi]

A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window BufferYuichiro Murachi, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto. ieicet, 91-C(4):465-478, 2008. [doi]

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture RecognitionYuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Masahiko Yoshimoto. ieicet, 91-C(4):457-464, 2008. [doi]

2006

A two-port SRAM for real-time video processor saving 53 of bitline power with majority logic and data-bit reorderingHidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto. islped 2006: 61-66 [doi]

VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video SegmentationNoriyuki Minegishi, Junichi Miyakoshi, Yuki Kuroda, Tadayoshi Katagiri, Yuki Fukuyama, Ryo Yamamoto, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto. ieicet, 89-C(3):230-242, 2006. [doi]

A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video ProcessingJunichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno. vlsi 2006: 192-197 [doi]

A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video ProcessingJunichi Miyakoshi, Yuichiro Murachi, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto. ieicet, 89-C(11):1629-1636, 2006. [doi]

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array ArchitectureJunichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto. ieicet, 89-A(12):3623-3633, 2006. [doi]

A 0.3-V Operating, ::::V::::::th::-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and BeyondYasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto. ieicet, 89-A(12):3634-3641, 2006. [doi]

2005

A Low-Power Systolic Array Architecture for Block-Matching Motion EstimationJunichi Miyakoshi, Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Masayuki Miyama, Masahiko Yoshimoto. ieicet, 88-C(4):559-569, 2005. [doi]

A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video ApplicationYuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Junichi Miyakoshi, Masayuki Miyama, Masahiko Yoshimoto. ieicet, 88-A(12):3492-3499, 2005. [doi]

2004

A sub-mW MPEG-4 motion estimation processor core for mobile video applicationYuki Kuroda, Junichi Miyakoshi, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto. aspdac 2004: 527-528 [doi]

A sub-mW MPEG-4 motion estimation processor core for mobile video applicationMasayuki Miyama, Junichi Miyakoshi, Yuki Kuroda, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto. jssc, 39(9):1562-1570, 2004. [doi]

2003

A sub-mW MPEG-4 motion estimation processor core for mobile video applicationJunichi Miyakoshi, Yuri Kuroda, Masayuki Miyama, Kosuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto. cicc 2003: 181-184 [doi]

2002

An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithmMasayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto. cicc 2002: 167-170 [doi]

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2023

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2002

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