Katarzyna Radecka - researchr alias

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Viewing Publication 1 - 64 from 64

2022

Wearable Vibrotactile System as an Assistive Technology SolutionMajid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic. monet, 27(2):709-717, 2022. [doi]

2019

Exploring Better Food Detection via Transfer LearningJianing Sun, Katarzyna Radecka, Zeljko Zilic. mva 2019: 1-6 [doi]

2017

2016

Respiration Disorders Classification With Informative Features for m-Health ApplicationsAtena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic. titb, 20(3):733-747, 2016. [doi]

Haptic feedback and human performance in a wearable sensor systemMajid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic. bhi 2016: 620-624 [doi]

2015

2014

A Medical Cloud-Based Platform for Respiration Rate Measurement and Hierarchical Classification of Breath DisordersAtena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic. sensors, 14(6):11204-11224, 2014. [doi]

Design of an e-Health Respiration and Body Posture Monitoring System and Its Application for Rib Cage and Abdomen Synchrony AnalysisAtena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic. bibe 2014: 141-148 [doi]

Development of a Remote Monitoring System for Respiratory AnalysisAtena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic. iot360 2015: 193-202 [doi]

Multi-sensor blind recalibration in mHealth applicationsAtena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic. ihtc 2014: 1-4 [doi]

Tidal volume variability and respiration rate estimation using a wearable accelerometer sensorAtena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic. mobihealth 2014: 1-6 [doi]

Automated diagnosis of knee pathology using sensory dataMajid Janidarmian, Katarzyna Radecka, Zeljko Zilic. mobihealth 2014: 95-98 [doi]

Affordable erehabilitation monitoring platformMajid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic. ihtc 2014: 1-6 [doi]

A hybrid arithmetic transform for precision analysis of floating-point polynomial specificationsO. Sarbishei, Katarzyna Radecka, Zeljko Zilic. newcas 2014: 37-40 [doi]

2013

SAR Computation and Channel Modeling of Body Area NetworkYu Pang, Qian Lei, Jinzhao Lin, Zhiyong Luo, Zhangyong Li, Zeljko Zilic, Katarzyna Radecka. bodynets 2013: 120-123 [doi]

On the Fixed-Point Accuracy Analysis and Optimization of Polynomial SpecificationsOmid Sarbishei, Katarzyna Radecka. tcad, 32(6):831-844, 2013. [doi]

A minimum MSE sensor fusion algorithm with tolerance to multiple faultsOmid Sarbishei, Atena Roshan Fekr, Majid Janidarmian, Benjamin Nahill, Katarzyna Radecka. ets 2013: 1 [doi]

An efficient fault-tolerant sensor fusion algorithm for accelerometersOmid Sarbishei, Benjamin Nahill, Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic, Boris Karajica. bsn 2013: 1-6 [doi]

SAT-based reversible gate/wire replacement fault testingSayeeda Sultana, Atena Roshan Fekr, Katarzyna Radecka. mwscas 2013: 1075-1078 [doi]

Testing reversible adder/subtractor for missing control pointsSayeeda Sultana, Katarzyna Radecka. mwscas 2013: 412-415 [doi]

2012

2011

A novel method of synthesizing reversible logicYu Pang, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka. iscas 2011: 2857-2860 [doi]

An efficient algorithm of performing range analysis for fixed-point arithmetic circuits based on SAT checkingYu Pang, Katarzyna Radecka. iscas 2011: 1736-1739 [doi]

Positive Davio-based synthesis algorithm for reversible logicYu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka. iccd 2011: 212-218 [doi]

An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuitsYu Pang, Katarzyna Radecka, Zeljko Zilic. aspdac 2011: 455-460 [doi]

Analysis of Mean-Square-Error (MSE) for fixed-point FFT unitsO. Sarbishei, Katarzyna Radecka. iscas 2011: 1732-1735 [doi]

On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC MultipliersOmid Sarbishei, Katarzyna Radecka. arith 2011: 62-69 [doi]

Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible NetworkSayeeda Sultana, Katarzyna Radecka. ismvl 2011: 147-152 [doi]

A study on relating redundancy removal in classical circuits to reversible mappingSayeeda Sultana, Katarzyna Radecka, Yu Pang. iccd 2011: 206-211 [doi]

Reversible implementation of square-root circuitSayeeda Sultana, Katarzyna Radecka. icecsys 2011: 141-144 [doi]

Fault tolerant glucose sensor readout and recalibrationZeljko Zilic, Katarzyna Radecka. wh 2011: 35 [doi]

2010

2008

Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transformYu Pang, Katarzyna Radecka. dac 2008: 397-402 [doi]

Design for Testability of QCA Logic Under Stuck-at-value Fault ModelSayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka. mvl, 14(1-2):145-176, 2008. [doi]

2007

Adiabatic Implementation of Reversible Logic Circuits in CMOS TechnologyAli Khazamipour, Katarzyna Radecka. mvl, 13(1-2):191-216, 2007. [doi]

Scaling and Better Approximating Quantum Fourier Transform by Higher RadicesZeljko Zilic, Katarzyna Radecka. TC, 56(2):202-207, 2007. [doi]

Reversible circuit technology mapping from non-reversible specificationsZeljko Zilic, Katarzyna Radecka, Ali Kazamiphur. date 2007: 558-563 [doi]

2006

2004

Architectures of Increased Availability Wireless Sensor Network NodesMan Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka. itc 2003: 1232-1241 [doi]

FPGA Emulation of Quantum CircuitsAhmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka. iccd 2004: 310-315 [doi]

Design Verification by Test Vectors and Arithmetic Transform Universal Test SetKatarzyna Radecka, Zeljko Zilic. TC, 53(5):628-640, 2004. [doi]

2002

Specifying and verifying imprecise sequential datapaths by Arithmetic TransformsKatarzyna Radecka, Zeljko Zilic. iccad 2002: 128-131 [doi]

Identifying Redundant Wire Replacements for Synthesis and VerificationKatarzyna Radecka, Zeljko Zilic. vlsid 2002: 517-523 [doi]

The Role of Super-Fast Transforms in Speeding Up Quantum ComputationsZeljko Zilic, Katarzyna Radecka. ismvl 2002: 129-135 [doi]

2001

Arithmetic Transforms for Verifying Compositions of Sequential DatapathsKatarzyna Radecka, Zeljko Zilic. iccd 2001: 348-353

Combinational verification by simulations, SAT and BDDsKatarzyna Radecka, Zeljko Zilic, Karim Khordoc. icecsys 2001: 1627-1630 [doi]

: Identifying redundant gate replacements in verification by error modelingZeljko Zilic, Katarzyna Radecka. itc 2001: 803-812

2000

Using Arithmetic Transform for Verification of Datapath Circuits via Error ModelingKatarzyna Radecka, Zeljko Zilic. vts 2000: 271-280 [doi]

1999

On Feasible Multivariate Polynomial Interpolations over Arbitrary FieldsZeljko Zilic, Katarzyna Radecka. issac 1999: 67-74 [doi]

1997

Arithmetic built-in self-test for DSP coresKatarzyna Radecka, Janusz Rajski, Jerzy Tyszer. tcad, 16(11):1358-1369, 1997. [doi]

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2022

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