Kenneth D. Wagner - researchr alias

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Viewing Publication 1 - 13 from 13

2005

Keeping current with silicon and systems technology in the mid-90sKenneth D. Wagner. dt, 22(1):7-9, 2005. [doi]

1999

Robust Scan-Based Logic Test in VDSM TechnologiesKenneth D. Wagner. Computer, 32(11):66-74, 1999.

1998

Design for Testability Techniques at the Behavioral and Register-Transfer LevelsSujit Dey, Anand Raghunathan, Kenneth D. Wagner. et, 13(2):79-91, 1998. [doi]

1996

EIC MessageKenneth D. Wagner, Yervant Zorian. dt, 13(2):2, 1996.

High-Level Synthesis for Testability: A Survey and PerspectiveKenneth D. Wagner, Sujit Dey. dac 1996: 131-136 [doi]

1993

Testable Programmable Digital Clock Pulse Control ElementsKenneth D. Wagner, Bernd Könemann. itc 1993: 902-909

1991

Enhancing Board Functional Self-Test by Concurrent SamplingKenneth D. Wagner, Thomas W. Williams. itc 1991: 633-640

1990

Guest Editorial: The Many Faces of TestKenneth D. Wagner. dt, 7(4):4, 1990.

1988

Probability models for pseudorandom test sequencesEdward J. McCluskey, Samy Makar, Samiha Mourad, Kenneth D. Wagner. tcad, 7(1):68-74, 1988. [doi]

Design for Testability of Mixed Signal Integrated CircuitsKenneth D. Wagner, Thomas W. Williams. itc 1988: 823-828

Clock system designKenneth D. Wagner. dt, 5(5):9-27, 1988. [doi]

1987

Pseudorandom TestingKenneth D. Wagner, Cary K. Chin, Edward J. McCluskey. TC, 36(3):332-343, 1987.

1985

The Error Latency of Delay Faults in Combinational and Sequential CircuitsKenneth D. Wagner. itc 1985: 334-341

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