Kevin J. Nowka - researchr alias

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Viewing Publication 1 - 56 from 56

2023

A Deep Transfer Learning based approach for forecasting spatio-temporal features to maximize yield in cotton cropsKrishna Chaitanya Gadepally, Sambandh Bhusan Dhal, Mahendra Bhandari, Juan Landivar, Stavros Kalafatis, Kevin J. Nowka. ciss 2023: 1-4 [doi]

2015

Second-Generation Big Data SystemsFadi H. Gebara, H. Peter Hofstee, Kevin J. Nowka. Computer, 48(1):36-41, 2015. [doi]

2012

Transforming memory systems: Optimizing for client value on emerging workloadsKevin J. Nowka. vlsi-dat 2012: 1-2 [doi]

2011

The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAMJente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Thomas Fröhnel, Sudesh Saroop, Sani R. Nassif, Kevin J. Nowka. tcas, 58-I(9):2010-2016, 2011. [doi]

2010

2009

Statistical yield analysis of silicon-on-insulator embedded DRAMRouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, W. Reohr, Sani R. Nassif, Kevin J. Nowka. isqed 2009: 190-194 [doi]

2008

Performance-Optimized Design for Parametric ReliabilityRamyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka. et, 24(1-3):129-141, 2008. [doi]

Circuit Techniques Utilizing Independent Gate Control in Double-Gate TechnologiesJente B. Kuang, Keunwoo Kim, Ching-Te Chuang, Hung C. Ngo, F. H. Gebara, Kevin J. Nowka. tvlsi, 16(12):1657-1665, 2008. [doi]

An on-chip dual supply charge pump system for 45nm PD SOI eDRAMJente B. Kuang, A. Mathews, J. Barth, Fadi H. Gebara, T. Nguyen, Jeremy D. Schaub, Kevin J. Nowka, Gary D. Carpenter, Don Plass, E. Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata. esscirc 2008: 66-69 [doi]

Characterization and design for variability and reliabilityKevin J. Nowka, Sani R. Nassif, Kanak Agarwal. cicc 2008: 341-346 [doi]

A Design Model for Random Process VariabilityVictoria Wang, Kanak Agarwal, Sani R. Nassif, Kevin J. Nowka, Dejan Markovic. isqed 2008: 734-737 [doi]

2007

2006

Power Gating with Multiple Sleep ModesKanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester. isqed 2006: 633-637 [doi]

Adaptive Design for Performance-Optimized RobustnessRamyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka. dft 2006: 3-11 [doi]

A Scheme for On-Chip Timing CharacterizationRamyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham. vts 2006: 24-29 [doi]

Fine grained multi-threshold CMOS for enhanced leakage reductionHarmander Deogun, Dennis Sylvester, Kevin J. Nowka. iscas 2006: [doi]

A dual-V::DD:: boosted pulsed bus technique for low power and low leakage operationHarmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka. islped 2006: 73-78 [doi]

SRAM Local Bit Line Access Failure AnalysesPraveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif. isqed 2006: 204-209 [doi]

Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display SystemsJayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown. vlsid 2006: 89-93 [doi]

Circuit Design Style for Energy Efficiency: LSDL and Compound DominoXiao Yan-Yu, Robert K. Montoye, Kevin J. Nowka, Bart R. Zeydel, Vojin G. Oklobdzija. patmos 2006: 47-55 [doi]

2005

Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strengthHarmander Singh Deogun, Dennis Sylvester, Rahul M. Rao, Kevin J. Nowka. socc 2005: 147-150 [doi]

Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk MinimizationHarmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka. isqed 2005: 88-93 [doi]

A Low-Overhead Virtual Rail Technique for SRAM Leakage Power ReductionJente B. Kuang, Hung C. Ngo, Kevin J. Nowka, J. C. Law, Rajiv V. Joshi. iccd 2005: 574-584 [doi]

Parametric Yield Analysis and Constrained-Based Supply Voltage OptimizationRahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown. isqed 2005: 284-290 [doi]

Guest Editors Introduction: New Dimensions in 3D IntegrationSachin S. Sapatnekar, Kevin J. Nowka. dt, 22(6):496-497, 2005. [doi]

Controlled-Load Limited Switch Dynamic Logic CircuitJayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown. isqed 2005: 83-87 [doi]

2004

2003

Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOIAlan J. Drake, Kevin J. Nowka, Richard B. Brown. vlsi 2003: 263

Resonant clocking using distributed parasitic capacitanceAlan J. Drake, Kevin J. Nowka, Tuyet Nguyen, Jeffrey L. Bums, Richard B. Brown. cicc 2003: 647-650 [doi]

The design and application of the PowerPC 405LP energy-efficient system-on-a-chipKevin J. Nowka, Gary D. Carpenter, Bishop Brock. ibmrd, 47(5-6):631-640, 2003. [doi]

2002

A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor CellsOhsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr.. vlsisp, 31(2):77-89, 2002. [doi]

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scalingKevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop Brock, Koji I. Ishii, Tuyet Nguyen, Jeffrey L. Burns. jssc, 37(11):1441-1447, 2002. [doi]

2001

Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variationHoang Q. Dao, Kevin J. Nowka, Vojin G. Oklobdzija. islped 2001: 56-59 [doi]

A fast hybrid carry-lookahead/carry-select adder designOhsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka. glvlsi 2001: 149-152 [doi]

Leading Zero Anticipation and Detection-A Comparison of MethodsMartin S. Schmookler, Kevin J. Nowka. arith 2001: 7-12 [doi]

2000

1999

Beyond 1 GHzH. Peter Hofstee, Kevin J. Nowka. cicc 1999: 57-61 [doi]

1998

High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz MicroprocessorDavid F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin G. Stawiasz. vts 1998: 234-238 [doi]

Designing for a gigahertz [guTS integer processor]H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi. micro, 18(3):66-74, 1998. [doi]

Circuit design techniques for a gigahertz integer microprocessorKevin J. Nowka, Tibi Galambos. In ICCD. 1998: 11-16 [doi]

Design methodology for a 1.0 GHz microprocessorStephen D. Posluszny, N. Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, K. Lee, D. Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo. In ICCD. 1998: 17-23 [doi]

1997

Circuits and Microarchitecture for Gigahertz VLSI DesignsKevin J. Nowka, H. Peter Hofstee. arvlsi 1997: 284-287 [doi]

1995

The SNAP Project: Towards Sub-Nanosecond ArithmeticMichael J. Flynn, Kevin J. Nowka, G. Bewick, Eric M. Schwarz, Nhon T. Quach. arith 1995: 75 [doi]

System Design Using Wave-Pipelining: A CMOS VLSI Vector UnitKevin J. Nowka, Michael J. Flynn. iscas 1995: 2301-2304

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