Ki Chul Chun - researchr alias

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Viewing Publication 1 - 20 from 20

2021

2020

2018

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM processKi Chul Chun, Yong-Gyu Chu, Jin-Seok Heo, Tae Sung Kim, Soohwan Kim, Hui-Kap Yang, Mi-Jo Kim, Chang-Kyo Lee, Ju-Hwan Kim, Hyunchul Yoon, Chang-Ho Shin, Sang-uhn Cha, Hyung Jin Kim, Young-Sik Kim, Kyungryun Kim, Young-Ju Kim, Won Jun Choi, Dae-Sik Yim, Inkyu Moon, Young-Ju Kim 0001, Junha Lee, Young Choi, Yongmin Kwon, Sung-Won Choi, Jung-Wook Kim, Yoon-Suk Park, Woongdae Kang, Jinil Chung, Seunghyun Kim, Yesin Ryu, Seong Jin Cho, Hoon Shin, Hangyun Jung, Sanghyuk Kwon, Kyuchang Kang, Jongmyung Lee, Yujung Song, Young-Jae Kim, Eun-Ah Kim, Kyung-Soo Ha, Kyoung-Ho Kim, Seok-Hun Hyun, Seung Bum Ko, Jung Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang. isscc 2018: 206-208 [doi]

2014

A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory ApplicationsSeung-hwan Song, Ki Chul Chun, Chris H. Kim. jssc, 49(8):1861-1871, 2014. [doi]

2013

A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power ModeWei Zhang 0032, Ki Chul Chun, Chris H. Kim. tcas, 60-I(8):2030-2038, 2013. [doi]

A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache MemoryKi Chul Chun, Hui Zhao, Jonathan D. Harms, Tae-Hyoung Kim, Jian-Ping Wang, Chris H. Kim. jssc, 48(2):598-610, 2013. [doi]

A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applicationsSeung-hwan Song, Ki Chul Chun, Chris H. Kim. cicc 2013: 1-4 [doi]

A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh SchemeSeung-hwan Song, Ki Chul Chun, Chris H. Kim. jssc, 48(5):1302-1314, 2013. [doi]

2012

2011

A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted suppliesKi Chul Chun, Wei Zhang 0032, Pulkit Jain, Chris H. Kim. isscc 2011: 506-507 [doi]

A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die CachesKi Chul Chun, Pulkit Jain, Jung Hwa Lee, Chris H. Kim. jssc, 46(6):1495-1505, 2011. [doi]

2010

Logic-compatible embedded DRAM design for memory intensive low power systemsKi Chul Chun, Pulkit Jain, Chris H. Kim. iscas 2010: 277-280 [doi]

Variation aware performance analysis of gain cell embedded DRAMsWei Zhang, Ki Chul Chun, Chris H. Kim. islped 2010: 19-24 [doi]

2009

A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53 less static power than a power-gated SRAMKi Chul Chun, Pulkit Jain, Chris H. Kim. islped 2009: 119-120 [doi]

2004

Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMsJae-Yoon Sim, Kee-Won Kwon, Ki Chul Chun. jssc, 39(4):694-703, 2004. [doi]

2003

A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensorJae-Yoon Sim, Hongil Yoon, Ki Chul Chun, Hyun-Seok Lee, Sang Pyo Hong, Kyu-Chan Lee, Jei-Hwan Yoo, Dong Il Seo, Soo-In Cho. jssc, 38(4):631-640, 2003. [doi]

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