Koichiro Mashiko - researchr alias

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Viewing Publication 1 - 19 from 19

2019

Evaluation of SRAM PUF Characteristics and Generation of Stable Bits for IoT SecurityPyi Phyo Aung, Koichiro Mashiko, Nordinah Binti Ismail, Chia Yee Ooi. irict 2020: 441-450 [doi]

2007

A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA AlgorithmHao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada. ieicet, 90-C(6):1181-1188, 2007. [doi]

2006

2000

A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 /spl mu/m SOI-CMOS technologyToru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara. jssc, 35(5):751-756, 2000. [doi]

1997

1996

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architectureHiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko. jssc, 31(6):773-783, 1996. [doi]

How to design low-power digital cellular phonesKoichiro Mashiko. islped 1996: 177-180 [doi]

1995

A BiCMOS wired-OR logicYasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko. jssc, 30(6):622-628, June 1995. [doi]

1994

A voltage compensated series-gate bipolar circuit operating at sub-2 VHisayasu Sato, Kimio Ueda, Nagisa Sasaki, Tatsuhiko Ikeda, Koichiro Mashiko. jssc, 29(10):1200-1205, October 1994. [doi]

1991

A self-learning neural network chip with 125 neurons and 10 K self-organization synapsesYutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Harufusa Kondoh, Shimpei Kayano. jssc, 26(4):607-611, April 1991. [doi]

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architectureYutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Hiromi Notani, Harufusa Kondoh, Shinpei Kayano. jssc, 26(11):1637-1644, November 1991. [doi]

A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gatesToshiaki Hanibuchi, Masahiro Ueda, Keiichi Higashitani, Masahiro Hatanaka, Koichiro Mashiko, Akiharu Tada. jssc, 26(3):427-431, March 1991. [doi]

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swingYasunobu Nakase, Kakutaro Suda, Koichiro Mashiko, Tatsuhiko Ikeda, Shinpei Kayano. jssc, 26(4):518-524, April 1991. [doi]

1990

A speed-enhanced DRAM array architecture with embedded ECCKazutami Arimoto, Yoshio Matsuda, Kiyohiro Furutani, Masaki Tsukude, Tsukasa Ooishi, Koichiro Mashiko, Kuzuyasu Fujishima. jssc, 25(1):11-17, February 1990. [doi]

1989

A built-in Hamming code ECC circuit for DRAMsKiyohiro Furutani, Kazutami Arimoto, Hiroshi Miyamoto, Toshifumi Kobayashi, Kenichi Yasuda, Koichiro Mashiko. jssc, 24(1):50-56, February 1989. [doi]

1985

Test Pattern Considerations for Fault Tolerant High Density DRAMHiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, T. Nakano. itc 1985: 451-455

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