Krishnaswamy Nagaraj - researchr alias

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Viewing Publication 1 - 25 from 25

2021

Fault-based Built-in Self-test and Evaluation of Phase Locked LoopsMehmet Ince, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, LeRoy Winemberg, Sule Ozev. todaes, 26(3), 2021. [doi]

2019

Digital Built-in Self-Test for Phased Locked Loops to Enable Fault DetectionMehmet Ince, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, LeRoy Winemberg, Sule Ozev. ets 2019: 1-6 [doi]

2017

2 SAR ADC in 65nm using novel residue boostingJoonsung Park, Krishnaswamy Nagaraj, Mikel Ash, Ajay Kumar. cicc 2017: 1-4 [doi]

2016

An oxide electrothermal filter in standard CMOSLorenzo Pedala, Ugur Sonmez, Fabio Sebastiano, Kofi A. A. Makinwa, Krishnaswamy Nagaraj, Joonsung Park. ieeesensors 2016: 1-3 [doi]

2015

°CXiao Pu, Mikel Ash, Krishnaswamy Nagaraj, Joonsung Park, Steve Vu, Paul Kimelman, Sean de la Haye. jssc, 50(9):2127-2137, 2015. [doi]

2014

A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADCAmit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan. mwscas 2014: 1053-1056 [doi]

Corrections to "Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference"Xiao Pu, Ajay Kumar, Krishnaswamy Nagaraj. tcas, 61(8):639, 2014. [doi]

2013

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock LoopsKrishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun. tcas, 60-I(3):517-528, 2013. [doi]

2012

A Novel fractional-n PLL Based on a Simple Reference MultiplierXiao Pu, Krishnaswamy Nagaraj, Jacob Abraham, Axel Thomsen. jcsc, 21(6), 2012. [doi]

Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency ReferenceXiao Pu, Ajay Kumar, Krishnaswamy Nagaraj. tcas, 59-II(6):331-335, 2012. [doi]

2007

New Associate EditorKrishnaswamy Nagaraj. jssc, 42(5):951, 2007. [doi]

New Associate EditorKrishnaswamy Nagaraj. jssc, 42(6):1195, 2007. [doi]

Message from the Outgoing Editor-in-ChiefKrishnaswamy Nagaraj. jssc, 42(8):1631, 2007. [doi]

New Associate EditorsKrishnaswamy Nagaraj. jssc, 42(7):1451-1452, 2007. [doi]

New Associate EditorKrishnaswamy Nagaraj. jssc, 42(4):719, 2007. [doi]

2005

New Associate EditorKrishnaswamy Nagaraj. jssc, 40(3):575, 2005. [doi]

New Associate EditorKrishnaswamy Nagaraj. jssc, 40(2):359, 2005. [doi]

New Associate EditorKrishnaswamy Nagaraj. jssc, 40(6):1211, 2005. [doi]

2004

EditorialKrishnaswamy Nagaraj. jssc, 39(8):1220, 2004. [doi]

2001

A 165 MS/s 8-bit CMOS A/D converter with background offset cancellationGennady Feygin, Krishnaswamy Nagaraj, Ranjan Chattopadhyay, R. Herrera, I. Papantonopoulos, David A. Martin, P. Wu, Shanthi Pavan. cicc 2001: 153-156 [doi]

2000

A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-/spl mu/m digital CMOS processKrishnaswamy Nagaraj, David A. Martin, Mark Wolfe, Ranjan Chattopadhyay, Shanthi Pavan, Jason Cancio, T. R. Viswanathan. jssc, 35(12):1760-1768, 2000. [doi]

Widely programmable high-frequency continuous-time filters in digital CMOS technologyShanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj. jssc, 35(4):503-511, 2000. [doi]

1997

A 160-MHz analog equalizer for magnetic disk read ChannelSami Kiriaki, T. Lakshmi Viswanathan, Gennady Feygin, Robert Bogdan Staszewski, Richard Pierson, Bill Krenik, Michiel de Wit, Krishnaswamy Nagaraj. jssc, 32(11):1858-1865, 1997. [doi]

A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiersKrishnaswamy Nagaraj, H. Scott Fetterman, Joseph Anidjar, Stephen H. Lewis, Robert G. Renninger. jssc, 32(3):312-320, 1997. [doi]

1995

A low supply voltage high PSRR voltage reference in CMOS processKhong-Meng Tham, Krishnaswamy Nagaraj. jssc, 30(5):586-590, May 1995. [doi]

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