Lawrence T. Pillage - researchr alias

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Viewing Publication 1 - 23 from 23

2013

Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing"Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan 0001, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li 0001, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman. jssc, 48(6):1539, June 2013. [doi]

1994

Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applicationsDemos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage. tcad, 13(6):729-736, 1994. [doi]

Predicting Circuit Performance Using Circuit-level Statistical Timing AnalysisRonn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer. eurodac 1994: 332-337

A Gate-Delay Model for high-Speed CMOS CircuitsFlorentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage. dac 1994: 576-580 [doi]

OTTER: Optimal Termination of Transmission Lines Excluding RadiationRohini Gupta, Lawrence T. Pillage. dac 1994: 640-645 [doi]

Domain Characterization of Transmission Line Models for Efficient SimulationRohini Gupta, Seok-Yoon Kim, Lawrence T. Pillage. iccd 1994: 558-562

Time-domain macromodels for VLSI interconnect analysisSeok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage. tcad, 13(10):1257-1270, 1994. [doi]

RC interconnect synthesis-a moment fitting approachNoel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage. iccad 1994: 418-425 [doi]

Modeling the Effective capacitance for the RC interconnect of CMOS gatesJessica Qian, Satyamurthy Pullela, Lawrence T. Pillage. tcad, 13(12):1526-1535, 1994. [doi]

RICE: rapid interconnect circuit evaluation using AWECurtis L. Ratzlaff, Lawrence T. Pillage. tcad, 13(6):763-776, 1994. [doi]

1993

1992

1991

Evaluating RC-Interconnect Using Moment-Matching ApproximationsNanda Gopal, Dean P. Neikirk, Lawrence T. Pillage. iccad 1991: 74-77

RICE: Rapid Interconnect Circuit EvaluatorCurtis L. Ratzlaff, Nanda Gopal, Lawrence T. Pillage. dac 1991: 555-560 [doi]

1990

DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay EvaluationDouglas R. Holberg, Santanu Dutta, Lawrence T. Pillage. iccad 1990: 546-549

Asymptotic waveform evaluation for timing analysisLawrence T. Pillage, Ronald A. Rohrer. tcad, 9(4):352-366, 1990. [doi]

1989

AWEsim: Asymptotic Waveform Evaluation for Timing AnalysisLawrence T. Pillage, Xueqing Huang, Ronald A. Rohrer. dac 1989: 634-637 [doi]

Efficient Final Placement Based on Nets-as-PointsXueqing Zhang, Lawrence T. Pillage, Ronald A. Rohrer. dac 1989: 578-581 [doi]

1988

A Quadratic Metric with a Simple Solution Scheme for Initial PlacementLawrence T. Pillage, Ronald A. Rohrer. dac 1988: 324-329 [doi]

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