Manuel Saldaña - researchr alias

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Viewing Publication 1 - 20 from 20

2016

Sidewinder: An Energy Efficient and Developer Friendly Heterogeneous Architecture for Continuous Mobile SensingDaniyal Liaqat, Silviu Jingoi, Eyal de Lara, Ashvin Goel, Wilson To, Kevin Lee, Italo De Moraes Garcia, Manuel Saldaña. asplos 2016: 205-215 [doi]

2014

Benefits of Adding Hardware Support for Broadcast and Reduce Operations in MPSoC ApplicationsYuanxi Peng, Manuel Saldaña, Christopher A. Madill, Xiaofeng Zou, Paul Chow. trets, 7(3):17, 2014. [doi]

2012

Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing PlatformsManuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow. ijrc, 2012, 2012. [doi]

2011

Hardware Support for Broadcast and Reduce in MPSoCYuanxi Peng, Manuel Saldaña, Paul Chow. fpl 2011: 144-150 [doi]

2010

2009

Programming the Nallatech Xeon + multi-FPGA heterogeneous platformPaul Chow, Manuel Saldaña, Arun Patel, Christopher A. Madill. hotchips 2009: 1-16 [doi]

The challenges of using an embedded MPI for hardware-based processing nodesDaniel Le Ly, Manuel Saldaña, Paul Chow. fpt 2009: 120-127 [doi]

A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing SystemsManuel Saldaña, Emanuel Ramalho, Paul Chow. ijrc, 2009, 2009. [doi]

2008

A profiler for a heterogeneous multi-core multi-FPGA systemDaniel Nunes, Manuel Saldaña, Paul Chow. fpt 2008: 113-120 [doi]

MPI as an abstraction for software-hardware interaction for HPRCsManuel Saldaña, Arun Patel, Christopher A. Madill, Daniel Nunes, Danyao Wang, Henry Styles, Andrew Putnam, Ralph Wittig, Paul Chow. sc 2008: 1-10 [doi]

2007

Routability of Network Topologies in FPGAsManuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow. tvlsi, 15(8):948-951, 2007. [doi]

2006

A Scalable FPGA-based MultiprocessorArun Patel, Christopher A. Madill, Manuel Saldaña, Chris Comis, Regis Pomes, Paul Chow. fccm 2006: 111-120 [doi]

The routability of multiprocessor network topologies in FPGAsManuel Saldaña, Lesley Shannon, Paul Chow. fpga 2006: 232 [doi]

TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAsManuel Saldaña, Paul Chow. fpl 2006: 1-6 [doi]

The routability of multiprocessor network topologies in FPGAsManuel Saldaña, Lesley Shannon, Paul Chow. slip 2006: 49-56 [doi]

Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPIManuel Saldaña, Daniel Nunes, Emanuel Ramalho, Paul Chow. reconfig 2006: 260-279 [doi]

A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design VerificationLesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow. fpl 2006: 1-6 [doi]

2005

Designing an FPGA SoC Using a Standardized IP Block InterfaceLesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow. fpt 2005: 341-342

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