Mitsuo Nakamura - researchr alias

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Viewing Publication 1 - 4 from 4

2018

An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay LinesNobutaro Shibata, Mitsuo Nakamura. ieicet, 101-A(8):1185-1196, 2018. [doi]

2013

Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOSKeiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Hiroshi Koizumi, Mitsuo Nakamura. mwscas 2013: 904-907 [doi]

A 280-MHz CMOS Intra-Symbol Intermittent RF Front End for Adaptive Power Reduction of Wireless Receivers According to Received-Signal Intensity in Sensor NetworksMitsuo Nakamura, Mamoru Ugajin, Mitsuru Harada. ieicet, 96-C(1):93-101, 2013. [doi]

2012

Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay controlKeiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Mitsuo Nakamura. mwscas 2012: 602-605 [doi]

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