Raúl Mateos - researchr alias

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Viewing Publication 1 - 19 from 19

2020

Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core SolutionRubén Nieto, Raúl Mateos, Álvaro Hernández. access, 8:188552-188563, 2020. [doi]

HW/SW Architecture for a Broadband Power-Line Communication System With LS Channel Estimator and ASCET EqualizerRubén Nieto, Raúl Mateos, Álvaro Hernández. tii, 16(11):6740-6749, 2020. [doi]

Evaluation of Software Inter-Processor Synchronization Methods for the Zynq-UltraScale+ ArchitectureRubén Nieto, Edel Díaz, Raúl Mateos, Álvaro Hernández. dcis 2020: 1-6 [doi]

2019

2018

Finite Precision Analysis of FPGA-based Architecture for FBMC Transmultiplexers in Broadband PLCRubén Nieto, Raúl Mateos, Álvaro Hernández. dcis 2018: 1-6 [doi]

FPGA-Based Architecture for Medium Access Techniques in Broadband PLCPablo Poudereux, Álvaro Hernández, Fernando Cruz-Roldán, Raúl Mateos. access, 6:9534-9542, 2018. [doi]

2016

Design of a filter bank multi-carrier system for broadband power line communicationsPablo Poudereux, Álvaro Hernández, Raúl Mateos, Freddy A. Pinto-Benel, Fernando Cruz-Roldán. sigpro, 128:57-67, 2016. [doi]

2015

Efficient Implementation of a Symbol Timing Estimator for Broadband PLCFrancisco Nombela, Enrique Garcia, Raúl Mateos, Álvaro Hernández. sensors, 15(8):20825-20844, 2015. [doi]

Study of suitable filter architectures for FBMC techniques applied to PLC communicationsPablo Poudereux, Raúl Mateos, Álvaro Hernández, Francisco Nombela, Fernando Cruz-Roldán. etfa 2015: 1-6 [doi]

2014

FPGA-based implementation of a filter bank-based transmultiplexer for multicarrier communicationsPablo Poudereux, Raúl Mateos, Álvaro Hernández, Fernando Cruz-Roldán, David Oses. etfa 2014: 1-6 [doi]

2013

Comparative of HLS and HDL implementations of a grid synchronization algorithmF. M. Sanchez, Raúl Mateos, Emilio José Bueno, J. Mingo, Ines Sanz. iecon 2013: 2232-2237 [doi]

2010

A Strict-Time Distributed Architecture for Digital Beamforming of Ultrasound SignalsJorge Camacho, Oscar Martinez, Montserrat Parrilla, Raúl Mateos, Carlos Fritsch. tim, 59(10):2716-2723, 2010. [doi]

2009

A DSP- and FPGA-Based Industrial Control With High-Speed Communication Interfaces for Grid Converters Applied to Distributed Power Generation SystemsEmilio José Bueno, Álvaro Hernández, Francisco J. Rodriguez, Carlos Giron, Raúl Mateos, Santiago Cobreces. tie, 56(3):654-669, 2009. [doi]

2004

Hardware/software co-simulation environment for CSoC with soft processorsRaúl Mateos, José Luis Lázaro, Felipe Espinosa. fpt 2004: 445-448 [doi]

2003

Different proposals to the multiplication of 3×3 vision mask in VHDL for FPGA'sIgnacio Bravo, A. Hernandez, Alfredo Gardel, Raúl Mateos, José Luis Lázaro, V. Diaz. etfa 2003: 208-211 [doi]

Lossless implementation in VHDL of an image wavelet transformRaúl Mateos, Alfredo Gardel, A. Hernandez, Ignacio Bravo, C. Garcia. etfa 2003: 195-198 [doi]

2001

Advanced and Intelligent Control Techniques Applied to the Drive Control and Path Tracking Systems on a Robotic WheelchairFelipe Espinosa, Elena López Guillén, Raúl Mateos, Manuel Mazo, Ricardo García. arobots, 11(2):137-148, 2001.

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