Rahul M. Rao - researchr alias

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Viewing Publication 1 - 38 from 38

2024

Late Breaking Results: Scan-Chain Optimization with Constrained Single Linkage Clustering and Geometry-Based Cluster BalancingGeorge Antony, Gireesh Kumar K. M, Naiju Karim Abdul, Rahul M. Rao. date 2024: 1-2 [doi]

2022

2021

2019

A Simulation-Based Metric to Guide Glitch Power Reduction in Digital CircuitsShivani Bathla, Rahul M. Rao, Nitin Chandrachoodan. tvlsi, 27(2):376-386, 2019. [doi]

2018

IBM POWER9 circuit design and energy optimization for 14-nm technologyEric J. Fluhr, Rahul M. Rao, Howard Smith, Alper Buyuktosunoglu, Ramon Bertran Monfort. ibmrd, 62(4/5):4, 2018. [doi]

A High Performance Gated Voltage Level Translator with Integrated MultiplexerDharshak B. S., Rahul M. Rao. vlsid 2018: 358-361 [doi]

Impact of Device Aging on Early Mode Failures in Pulsed LatchesAnkur Shukla, Rahul M. Rao, James D. Warnock. vlsid 2018: 256-260 [doi]

2017

2016

FVCAG: A framework for formal verification driven power modeling and verificationArun Joseph, Spandana Rachamalla, Rahul M. Rao, Anand Haridass, Pradeep Kumar Nalla. islped 2016: 260-265 [doi]

2013

Slew-Rate Monitoring Circuit for On-Chip Process Variation DetectionAmlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown. tvlsi, 21(9):1683-1692, 2013. [doi]

Extracting device-parameter variations using a single sensitivity-configurable ring oscillatorYuma Higuchi, Kenichi Shinkai, Masanori Hashimoto, Rahul M. Rao, Sani R. Nassif. ets 2013: 1-6 [doi]

2011

Variations: Sources and CharacterizationAditya Bansal, Rahul M. Rao. In Swarup Bhunia, Saibal Mukhopadhyay, editors, Low-Power Variation-Tolerant Design in Nanometer Silicon. pages 3-39, Springer, 2011. [doi]

SRAM Write-Ability Improvement With Transient Negative Bit-Line VoltageSaibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang. tvlsi, 19(1):24-32, 2011. [doi]

2010

Technology-circuit co-design of asymmetric SRAM cells for read stability improvementJae-Joon Kim, Rahul M. Rao, Keunwoo Kim. cicc 2010: 1-4 [doi]

Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk NoiseHarmander Singh, Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown. tvlsi, 18(1):166-170, 2010. [doi]

2009

2008

2007

Parametric Yield Analysis and Optimization in Leakage Dominated TechnologiesKanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown. tvlsi, 15(6):613-623, 2007. [doi]

2005

2004

Approaches to run-time and standby mode leakage reduction in global busesRahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif. islped 2004: 188-193 [doi]

Analysis and Optimization of Enhanced MTCMOS SchemeRahul M. Rao, Jeffrey L. Burns, Richard B. Brown. vlsid 2004: 234-239 [doi]

2003

1978

Frequency estimation by linear predictionLeland B. Jackson, Donald W. Tufts, Frank K. Soong, Rahul M. Rao. icassp 1978: 352-356 [doi]

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