Raymond Hoare - researchr alias

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Viewing Publication 1 - 17 from 17

2007

An automated, FPGA-based reconfigurable, low-power RFID tagAlex K. Jones, Raymond Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle. mam, 31(2):116-134, 2007. [doi]

2006

2005

2004

An 88-Way Multiprocessor within an FPGA with Customizable InstructionsRaymond Hoare, Shen Chih Tung, Katrina Werger. ipps 2004: [doi]

A 64-way VLIW/SIMD FPGA architecture and design flowAlex K. Jones, Raymond Hoare, Ivan S. Kourtev, Joshua Fazekas, Dara Kusic, John Foster, Sedric Boddie, Ahmed Muaydh. icecsys 2004: 499-502 [doi]

2003

Combining Mentor Graphics? HDL Designer FPGA Flow with a Reconfigurable System on a Programmable Chip, Educational Opportunity or Insanity?Raymond Hoare, Shen Chih Tung. mse 2003: 128-130 [doi]

2002

Cross-institutional assessment: Development and implementation of the On-line Student Survey SystemRaymond Hoare, Mary Besterfield-Sacre, Dan Ertman, Jessica Gerchak, Troy A. Johnson, Robert Shields, Larry J. Shuman. caee, 10(2):88-97, 2002. [doi]

An SoC Solution for Massive Parallel ProcessingDavid Reed, Raymond Hoare. ipps 2002: [doi]

2000

ClusterNet: An Object-Oriented Cluster NetworkRaymond Hoare. ipps 2000: 28-38 [doi]

1998

A Case for Aggregate NetworksRaymond Hoare, Henry G. Dietz. ipps 1998: 162-166 [doi]

1997

VLIW Across Multiple Superscalar Processors on a Single ChipSoohong P. Kim, Raymond Hoare, Henry G. Dietz. IEEEpact 1997: 166 [doi]

1996

A Fine-Grain Parallel Architecture Based on Barrier SynchronizationHenry G. Dietz, Raymond Hoare, Timothy Mattox. icpp 1996: 247-250

Bitwise aggregate networksRaymond Hoare, Henry G. Dietz, Timothy Mattox, Soohong P. Kim. spdp 1996: 306-313 [doi]

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