Raymond R. Hoare - researchr alias

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Viewing Publication 1 - 25 from 25

2014

Accelerating SAR processing on COTS FPGA hardware using C-to-gates design toolsRaymond R. Hoare, Denis Smetana. hpec 2014: 1-6 [doi]

2008

2007

Linking Compilation and Visualization for Massively Parallel ProgramsAlex K. Jones, Raymond R. Hoare, Joseph St. Onge, Joshua M. Lucas, Shuyi Shao, Rami G. Melhem. ipps 2007: 1-8 [doi]

2006

Interconnect routing and scheduling - Level-wise scheduling algorithm for fat tree interconnection networksZhu Ding, Raymond R. Hoare, Alex K. Jones, Rami G. Melhem. sc 2006: 96 [doi]

Interconnect routing and scheduling - A near-optimal real-time hardware scheduler for large cardinality crossbar switchesRaymond R. Hoare, Zhu Ding, Alex K. Jones. sc 2006: 94 [doi]

Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM)Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones. fccm 2006: 299-300 [doi]

Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware FunctionsRaymond R. Hoare, Alex K. Jones, Dara Kusic, Joshua Fazekas, John Foster, Shen Chih Tung, Michael L. McCloud. ejasp, 2006, 2006. [doi]

A Field Programmable RFID Tag and Associated Design FlowAlex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle. fccm 2006: 165-174 [doi]

An automated, reconfigurable, low-power RFID tagAlex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle. dac 2006: 131-136 [doi]

Passive active radio frequency identification tagsAlex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Peter J. Hawrylak, Leonid Mats, Raymond R. Hoare, James T. Cain, Marlin H. Mickle. ijrfita, 1(1):52-73, 2006. [doi]

A VLIW Processor With Hardware Functions: Increasing Performance While Reducing PowerAlex K. Jones, Raymond R. Hoare, Dara Kusic, Justin Stander, Gayatri Mehta, Joshua Fazekas. tcas, 53-II(11):1250-1254, 2006. [doi]

Design space exploration for low-power reconfigurable fabricsGayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones. ipps 2006: [doi]

A Low-Energy Reconfigurable Fabric for the SuperCISC ArchitectureGayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones. fccm 2006: 309-310 [doi]

A Low-Energy Reconfigurable Fabric for the SuperCISC ArchitectureGayatri Mehta, Justin Stander, Joshua M. Lucas, Raymond R. Hoare, Brady Hunsaker, Alex K. Jones. jolpe, 2(2):148-164, 2006. [doi]

Speech silicon AM: an FPGA-based acoustic modeling pipeline for hidden Markov model based speech recognitionJ. W. Schuster, K. Gupta, Raymond R. Hoare. ipps 2006: [doi]

A hybrid encoding scheme for efficient single-cycle range matching in content addressable memoryYing Yu, Raymond R. Hoare, Alex K. Jones, Ralph Sprang. iscas 2006: [doi]

2005

2004

LURU: global-scope FPGA technology mapping with content-addressable memoriesJoshua M. Lucas, Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones. icecsys 2004: 599-602 [doi]

2003

Short Courses in System-on-a-Chip (SoC) DesignIvan S. Kourtev, Raymond R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, David L. Landis. mse 2003: 126-127 [doi]

2002

A Width Expansion of MMX/SIMD Processing Architecture on an FPGARaymond R. Hoare, D. Swope, S. Bailey. pdcs 2002: 562-566

2001

Cyclical Cascade Chains: A Dynamic Barrier Synchronization Mechanism for Multiprocessor SystemsT. A. Johnson, Raymond R. Hoare. ipps 2001: 193

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