Ryu Ogiwara - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 10 from 10

2015

Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMsRyu Ogiwara, Daisaburo Takashima, Sumiko Doumae, Shinichiro Shiratake, Ryosuke Takizawa, Hidehiro Shiga. jssc, 50(5):1324-1331, 2015. [doi]

2011

2010

A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst ModeKatsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, T. Miyakawa, H. Shiga, S. M. Doumae, S. Ohtsuki, Y. Kumura, S. Shuto, T. Ozaki, K. Yamakawa, I. Kunishima, A. Nitayama, S. Fujii. tvlsi, 18(12):1745-1752, 2010. [doi]

2009

2006

A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst ModeKatsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, S. M. Doumae, S. Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii. isscc 2006: 459-466 [doi]

2003

2001

A 76-mm/sup 2/ 8-Mb chain ferroelectric memoryDaisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki. jssc, 36(11):1713-1720, 2001. [doi]

2000

A 0.5-/spl mu/m, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitorRyu Ogiwara, Sumio Tanaka, Yasuo Itoh, Tadashi Miyakawa, Yoshiaki Takeuchi, Sumiko Mano Doumae, Hiroyuki Takenaka, Iwao Kunishima, Susumu Shuto, Osamu Hidaka, Sumito Ohtsuki, Shin'ichi Tanaka. jssc, 35(4):545-551, 2000. [doi]

Sign in or sign up to see more results.

runs on WebDSL