Shao-Ku Kao - researchr alias

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Viewing Publication 1 - 19 from 19

2022

A Multipath Output-Capacitor-Less LDO RegulatorShao-Ku Kao, Jian-Jiun Chen, Chien-Hung Liao. access, 10:27185-27196, 2022. [doi]

2019

A programmbale 8-channel multiphase clock generator with 360 phases for focus ultrasound applicationsHsiang-Chi Cheng, Shih-Hung Cheng, Shao-Ku Kao. mj, 84:79-86, 2019. [doi]

2018

A 13.56 MHz CMOS High-Efficiency Active Rectifier With Dynamically Controllable Comparator for Biomedical Wireless Power Transfer SystemsHsiang-Chi Cheng, Cihun-Siyong Alex Gong, Shao-Ku Kao. access, 6:49979-49989, 2018. [doi]

2016

Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitorShao-Ku Kao, Yu-Zhang Lee, Chun-Yu Ku, Hsiang-Chi Cheng. mj, 56:134-141, 2016. [doi]

A self-calibrated delay-locked loop with low static phase errorShao-Ku Kao, Hsiang-Chi Cheng, Jian-Da Lin. ijcta, 44(4):929-944, 2016. [doi]

An all-digital DLL with duty-cycle correction using reusable TDCShao-Ku Kao, Yi-Hsien Hsieh, Hsiang-Chi Cheng. ijcta, 44(5):1055-1070, 2016. [doi]

2015

Pulsewidth control loop with a frequency detector for wide frequency range operationShao-Ku Kao, Hsiang-Chi Cheng, Yong-De You. mj, 46(4):291-297, 2015. [doi]

All-digital controlled boost DC-DC converter with all-digital DLL-based calibrationShao-Ku Kao, Jen-Hou Wu, Hsiang-Chi Cheng. mj, 46(10):970-980, 2015. [doi]

A fast-corrected all-digital DCC with synchronous input clockShao-Ku Kao, Sheng-Hung Hsueh. ijcta, 43(12):1845-1860, 2015. [doi]

2014

Frequency presetting and phase error detection technique for fast-locking phase-locked loopShao-Ku Kao. mj, 45(4):375-381, 2014. [doi]

A VCO-based phase-expanding conversion designed for time-domain data convertersShao-Ku Kao, Yi-Fu Tang, Hsiang-Chi Cheng. mj, 45(7):835-841, 2014. [doi]

2013

A delay-locked loop with self-calibration circuit for reducing phase errorShao-Ku Kao. mj, 44(8):663-669, 2013. [doi]

2011

Clock buffer with duty cycle correctorShao-Ku Kao, Yong-De You. mj, 42(5):740-744, 2011. [doi]

2010

Clock buffer with duty cycle correctorShao-Ku Kao, Yong-De You. socc 2010: 293-296 [doi]

2008

A Delay-Locked Loop With Statistical Background CalibrationShao-Ku Kao, Shen-Iuan Liu. tcas, 55-II(10):961-965, 2008. [doi]

2007

A 62.5-625-MHz Anti-Reset All-Digital Delay-Locked LoopShao-Ku Kao, Bo-Jiun Chen, Shen-Iuan Liu. tcas, 54-II(7):566-570, 2007. [doi]

2006

All-Digital Clock Deskew Buffer with Variable Duty CyclesShao-Ku Kao, Shen-Iuan Liu. ieicet, 89-C(6):753-760, 2006. [doi]

All-Digital Fast-Locked Synchronous Duty-Cycle CorrectorShao-Ku Kao, Shen-Iuan Liu. tcas, 53-II(12):1363-1367, 2006. [doi]

All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cyclesYou-Jen Wang, Shao-Ku Kao, Shen-Iuan Liu. jssc, 41(6):1262-1274, 2006. [doi]

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