Stephan Henzler - researchr alias

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Viewing Publication 1 - 20 from 20

2016

A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADCJunjie Kong, Stephan Henzler, Doris Schmitt-Landsiedel, Liter Siek. apccas 2016: 348-351 [doi]

2010

Digitalization of mixed-signal functionality in nanometer technologiesStephan Henzler. iccad 2010: 252-255 [doi]

2009

Adaptive circuit block model for power supply noise analysis of low power system-on-chipMatthias Eireiner, Doris Schmitt-Landsiedel, Paul Wallner, Andreas Schöne, Stephan Henzler, Ulrich Fiedler. issoc 2009: 13-18 [doi]

2008

2007

In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric VariationsMatthias Eireiner, Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel. jssc, 42(7):1583-1592, 2007. [doi]

Variation tolerant high resolution and low latency time-to-digital converterStephan Henzler, Siegmar Koeppe, Dominik Lorenz, Winfried Kamp, Ronald Kuenemund, Doris Schmitt-Landsiedel. esscirc 2007: 194-197 [doi]

2006

2005

Impact of process parameter variations on the energy dissipation in adiabatic logicJürgen Fischer, Ettore Amirante, Thomas Nirschl, Philip Teichmann, Stephan Henzler, Doris Schmitt-Landsiedel. ecctd 2005: 429-432 [doi]

Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuitsStephan Henzler, Thomas Nirschl, Matthias Eireiner, Ettore Amirante, Doris Schmitt-Landsiedel. cf 2005: 414-420 [doi]

Dynamic state-retention flip flop for fine-grained sleep-transistor schemeStephan Henzler, Thomas Nirschi, Christian Pacha, Peter Spindler, Philip Teichmann, Michael Fulde, Jürgen Fischer, Matthias Eireiner, Thomas Fischer, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel. esscirc 2005: 145-148 [doi]

Power-Clock Gating in Adiabatic Logic CircuitsPhilip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel. patmos 2005: 638-646 [doi]

2004

Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area ConsumptionStephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel. patmos 2004: 392-401 [doi]

Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched CircuitsStephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel. patmos 2004: 789-798 [doi]

2003

Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off SchemesStephan Henzler, Markus Koban, Doris Schmitt-Landsiedel, Jörg Berthold, Georg Georgakos. vlsi 2003: 246-251

Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off SchemesStephan Henzler, Philip Teichmann, Markus Koban, Jörg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel. vlsi 2006: 229-245 [doi]

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