Steven M. Burns - researchr alias

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Viewing Publication 1 - 45 from 45

2023

2022

2021

Machine Learning Techniques in Analog Layout AutomationTonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar. ispd 2021: 71-72 [doi]

ALIGN: A System for Automating Analog LayoutTonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar. dt, 38(2):8-18, 2021. [doi]

Common-Centroid Layouts for Analog Circuits: Advantages and LimitationsArvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar. date 2021: 1224-1229 [doi]

Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog CircuitsArvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar. iccad 2021: 1-9 [doi]

2020

2019

ALIGN: Open-Source Analog Layout Automation from the Ground UpKishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar. dac 2019: 77 [doi]

2018

A Template-Based Design Methodology for Graph-Parallel Hardware AcceleratorsAndrey Ayupov, Serif Yesil, Muhammet Mustafa Ozdal, Taemin Kim, Steven M. Burns, Ozcan Ozturk 0001. tcad, 37(2):420-430, 2018. [doi]

A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field GenerationMichael Barrow, Steven M. Burns, Ryan Kastner. fpl 2018: 335-342 [doi]

2017

Graph Analytics Accelerators for Cognitive SystemsMuhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, John Greth, Steven M. Burns, Ozcan Ozturk. micro, 37(1):42-51, 2017. [doi]

2016

Energy Efficient Architecture for Graph Analytics AcceleratorsMuhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, John Greth, Steven M. Burns, Özcan Özturk. isca 2016: 166-177 [doi]

2015

2013

An improved benchmark suite for the ISPD-2013 discrete cell sizing contestMuhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven M. Burns, Gustavo R. Wilke, Cheng Zhuo. ispd 2013: 168-170 [doi]

Trace alignment algorithms for offline workload analysis of heterogeneous architecturesMuhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa. iccad 2013: 654-661 [doi]

2012

The ISPD-2012 discrete cell sizing contest and benchmark suiteMuhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven M. Burns, Gustavo R. Wilke, Cheng Zhuo. ispd 2012: 161-164 [doi]

Algorithms for Gate Sizing and Device Parameter Selection for High-Performance DesignsMuhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu. tcad, 31(10):1558-1571, 2012. [doi]

2011

A trace compression algorithm targeting power estimation of long benchmarksAndrey Ayupov, Steven M. Burns. iccad 2011: 702-707 [doi]

Gate sizing and device technology selection algorithms for high-performance industrial designsMuhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu. iccad 2011: 724-731 [doi]

2007

Comparative Analysis of Conventional and Statistical Design TechniquesSteven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James Tschanz, Vivek De. dac 2007: 238-243 [doi]

2002

1999

Synthesis of asynchronous control circuits with automatically generated relative timing assumptionsJordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens. iccad 1999: 324-331 [doi]

CAD Directions for High Performance Asynchronous CircuitsKen S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken. dac 1999: 116-121 [doi]

1997

Bounded Delay Timing Analysis of a Class of CSP ProgramsHenrik Hulgaard, Steven M. Burns. fmsd, 11(3):265-294, 1997.

1996

General conditions for the decomposition of state holding elementsSteven M. Burns. async 1996: 48-57 [doi]

1995

The Triptych FPGA architectureGaetano Borriello, Carl Ebeling, Scott Hauck, Steven M. Burns. tvlsi, 3(4):491-501, 1995. [doi]

Placement and routing tools for the Triptych FPGACarl Ebeling, Larry McMurchie, Scott Hauck, Steven M. Burns. tvlsi, 3(4):473-482, 1995. [doi]

Efficient Timing Analysis of a Class of Petri NetsHenrik Hulgaard, Steven M. Burns. cav 1995: 423-436

An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent SystemsHenrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello. TC, 44(11):1306-1317, 1995. [doi]

Testing asynchronous circuits: A surveyHenrik Hulgaard, Steven M. Burns, Gaetano Borriello. integration, 19(3):111-131, 1995. [doi]

1994

An FPGA for Implementing Asynchronous CircuitsScott Hauck, Steven M. Burns, Gaetano Borriello, Carl Ebeling. dt, 11(3):60-69, 1994.

Bounded delay timing analysis of a class of CSP programs with choiceHenrik Hulgaard, Steven M. Burns. async 1994: 2-11 [doi]

1993

An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent SystemsTod Amon, Henrik Hulgaard, Steven M. Burns, Gaetano Borriello. iccd 1993: 166-173

Practical applications of an efficient time separation of events algorithmHenrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello. iccad 1993: 146-151 [doi]

1992

MONTAGNE: An FPL for Synchronous and Asynchronous CircuitsScott Hauck, Gaetano Borriello, Steven M. Burns, Carl Ebeling. fpga 1993: 44-51

1989

The first asynchronous microprocessor: the test resultsAlain J. Martin, Steven M. Burns, Tak-Kwan Lee, Drazen Borkovic, Pieter J. Hazewindus. sigarch, 17(4):95-98, 1989. [doi]

The design of an asynchronous microprocessorAlain J. Martin, Steven M. Burns, Tak-Kwan Lee, Drazen Borkovic, Pieter J. Hazewindus. sigarch, 17(4):99-110, 1989. [doi]

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1989

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