T. M. Mak - researchr alias

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Viewing Publication 1 - 64 from 64

2020

High-speed I/O capabilities added to military automatic test equipment (ATE) using synthetic instrumentsLouis Y. Ungar, Neil G. Jacobson, T. M. Mak. imm, 23(5):19-26, 2020. [doi]

2017

A Comprehensive BIST Solution for Polar Transceivers Using On-Chip ResourcesJae-woong Jeong, Vishwanath Natarajan, Shreyas Sen, T. M. Mak, Jennifer Kitchen, Sule Ozev. todaes, 23(1), 2017. [doi]

2015

Low-Cost On-Chip Clock Jitter Measurement SchemeMartin Omaña, Daniele Rossi, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Asifur Rahman, Simon Tam. tvlsi, 23(3):435-443, 2015. [doi]

2014

Innovative practices session 3C: Solving today's test challengesJohn Kim, Wolfgang Meyer, T. M. Mak, Amitava Majumdar. vts 2014: 1 [doi]

Interposer test: Testing PCBs that have shrunk 100xT. M. Mak. itc 2014: 1 [doi]

Clock Faults Induced Min and Max Delay ViolationsDaniele Rossi, Martin Omaña, José Manuel Cazeaux, Cecilia Metra, T. M. Mak. et, 30(1):111-123, 2014. [doi]

2013

Measurement of envelope/phase path delay skew and envelope path bandwidth in polar transmittersJae-woong Jeong, Sule Ozev, Shreyas Sen, T. M. Mak. vts 2013: 1-6 [doi]

2012

Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count ConstraintLi Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak. tvlsi, 20(9):1621-1633, 2012. [doi]

New Design for Testability Approach for Clock Fault TestingCecilia Metra, Martin Omaña, T. M. Mak, Simon Tam. TC, 61(4):448-457, 2012. [doi]

2011

Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance MicroprocessorsMartin Omaña, Cecilia Metra, T. M. Mak, Simon Tam. tvlsi, 19(12):2322-2325, 2011. [doi]

2010

On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock JitterMartin Omaña, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Simon Tam, Asifur Rahman. dft 2010: 265-272 [doi]

2009

Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraintLi Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak. iccad 2009: 191-196 [doi]

An industrial case study for X-canceling MISRJoon-Sung Yang, Nur A. Touba, Shih-yu Yang, T. M. Mak. itc 2009: 1-10 [doi]

2008

Jitters in high performance microprocessorsT. M. Mak. itc 2008: 1-6 [doi]

Novel On-Chip Clock Jitter Measurement Scheme for High Performance MicroprocessorsCecilia Metra, Martin Omaña, T. M. Mak, Asifur Rahman, Simon Tam. dft 2008: 465-473 [doi]

2007

The case for power with testT. M. Mak. dt, 24(3):296, 2007. [doi]

Infant Mortality--The Lesser Known Reliability IssueT. M. Mak. iolts 2007: 122 [doi]

Invited Talk 1: Testing of Power Constraint ComputingT. M. Mak. ats 2007: 6 [doi]

Novel compensation scheme for local clocks of high performance microprocessorsCecilia Metra, Martin Omaña, T. M. Mak, Simon Tam. itc 2007: 1-9 [doi]

Novel Approach to Clock Fault Testing for High Performance MicroprocessorsCecilia Metra, Martin Omaña, T. M. Mak, Simon Tam. vts 2007: 441-446 [doi]

Won t On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?Cecilia Metra, Daniele Rossi, T. M. Mak. TC, 56(3):415-428, 2007. [doi]

Data Recovery Block Design for Impulse Modulated Power Line Communications in a MicroprocessorRajesh Thirugnanam, Dong Sam Ha, T. M. Mak. isvlsi 2007: 153-158 [doi]

Design for Resilience to Soft Errors and VariationsMing Zhang, T. M. Mak, James Tschanz, Kee Sup Kim, Norbert Seifert, Davia Lu. iolts 2007: 23-28 [doi]

2006

Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware DesignMaryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak. vlsid 2006: 606-612 [doi]

Test Challenges for 3D CircuitsT. M. Mak. iolts 2006: 79 [doi]

Is System in Package the Panacea for Integration?T. M. Mak. dt, 23(3):256, 2006. [doi]

Guest Editors Introduction: Process Variation and Stochastic Design and TestT. M. Mak, Sani R. Nassif. dt, 23(6):436-437, 2006. [doi]

Should Logic SER be Solved at the Circuit Level?T. M. Mak, Subhasish Mitra. iolts 2006: 199 [doi]

Path (Min) Delay Faults and Their Impact on Self-Checking Circuits OperationCecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak. iolts 2006: 17-22 [doi]

Can Clock Faults be Detected Through Functional Test?Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak. ddecs 2006: 168-173

Soft Error Resilient System Design through Error CorrectionSubhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim. vlsi 2006: 332-337 [doi]

Soft Error Resilient System Design through Error CorrectionSubhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim. vlsi 2007: 143-156 [doi]

Test Consideration for Nanometer-Scale CMOS CircuitsKaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng. dt, 23(2):128-136, 2006. [doi]

Simulating the Effects of Process Variations on Capacitive CrosstalkArani Sinha, Shahin Nazarian, T. M. Mak. icecsys 2006: 604-607 [doi]

Sequential Element Design With Built-In Soft Error ResilienceMing Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, N. J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, S. J. Patel. tvlsi, 14(12):1368-1378, 2006. [doi]

2005

2004

Defect and Error Tolerance in the Presence of Massive Numbers of DefectsMelvin A. Breuer, Sandeep K. Gupta, T. M. Mak. dt, 21(3):216-227, 2004. [doi]

Trends in manufacturing test methods and their implicationsSandip Kundu, T. M. Mak, Rajesh Galivanche. itc 2003: 679-687 [doi]

A path-based methodology for post-silicon timing validationLeonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng. iccad 2004: 713-720 [doi]

Testing Gbps Interfaces without a Gigahertz TesterT. M. Mak, Mike Tripp, Anne Meixner. dt, 21(4):278-286, 2004. [doi]

New Challenges in Delay Testing of Nanometer, Multigigahertz DesignsT. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang. dt, 21(3):241-247, 2004. [doi]

Risks Associated with Faults within Test Pattern Compactors and Their Implications on TestingCecilia Metra, T. M. Mak, Martin Omaña. itc 2003: 1223-1231 [doi]

Are Our Design for Testability Features Fault Secure?Cecilia Metra, T. M. Mak, Martin Omaña. date 2004: 714-715 [doi]

Fault secureness need for next generation high performance microprocessor design for testability structuresCecilia Metra, T. M. Mak, Martin Omaña. cf 2004: 444-450 [doi]

Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing TestingCecilia Metra, Stefano Di Francescantonio, T. M. Mak. TC, 53(5):531-546, 2004. [doi]

Do We Need Anything More Than Single Bit Error Correction (ECC)?Michael Spica, T. M. Mak. mtdt 2004: 111-116 [doi]

Design considerations and DFT to enable testing of digital interfacesMike Tripp, T. M. Mak, Anne Meixner. cicc 2004: 197-205 [doi]

On path-based learning and its applications in delay test and diagnosisLi-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir. dac 2004: 492-497 [doi]

Testing of Hard Faults in Simultaneous Multithreaded ProcessorsEric F. Weglarz, Kewal K. Saluja, T. M. Mak. iolts 2004: 95-100 [doi]

2003

Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and MethodologiesAngela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak. itc 2003: 339-348 [doi]

Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault modelsAngela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak. dac 2003: 668-673 [doi]

Clock Calibration Faults and their Impact on Quality of High Performance MicroprocessorsCecilia Metra, T. M. Mak, Daniele Rossi. dft 2003: 63-70 [doi]

Embedded Tutorial: Test Consideration for Nanometer Scale CMOS CircuitsKaushik Roy, T. M. Mak, Kwang-Ting Cheng. vts 2003: 313-318 [doi]

Elimination of Traditional Functional Testing of Interface Timings at IntelMike Tripp, T. M. Mak, Anne Meixner. itc 2003: 1448-1456 [doi]

Elimination of Traditional Functional Testing of Interface Timings at IntelMike Tripp, T. M. Mak, Anne Meixner. itc 2003: 1014-1022 [doi]

2002

Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line TestingCecilia Metra, Stefano Di Francescantonio, T. M. Mak. itc 2002: 100-109 [doi]

2001

Crosstalk test generation on pseudo industrial circuits: a case studyLiang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer. itc 2001: 548-557

Evaluation of Clock Distribution Networks Most Likely Faults and Produced EffectsCecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak. dft 2001: 357-365 [doi]

1998

Cache RAM inductive fault analysis with fab defect modelingT. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, Joel Ferguson, Jianlin Yu. itc 1998: 862-871 [doi]

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1998

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