Tadeusz Kwasniewski - researchr alias

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Viewing Publication 1 - 18 from 18

2016

A reduced reference spur multiplying delay-locked loopXinjie Wang, Tadeusz Kwasniewski. ijcta, 44(8):1620-1627, 2016. [doi]

2015

A DLL fractional M/N frequency synthesizerHaizheng Guo, Tadeusz Kwasniewski. ccece 2015: 114-117 [doi]

A DLL-based period synthesisHaizheng Guo, Tadeusz Kwasniewski. ccece 2015: 103-106 [doi]

Low noise CMOS voltage-control oscillator design methodology with emphasis on non-linear effect contributions, 2.4 GHz CMOS design exampleZhe Jiang, Haizheng Guo, Tadeusz Kwasniewski. ccece 2015: 686-690 [doi]

2013

Spur analysis and reduction of edge combining DLL-based frequency multiplierHaizheng Guo, Xinjie Wang, Tadeusz Kwasniewski. ccece 2013: 1-4 [doi]

2012

Bang-Bang CDR's acquisition, locking, and jitter toleranceChao He, Tadeusz Kwasniewski. ccece 2012: 1-4 [doi]

A novel fractional-N PLL architecture with hybrid of DCO and VCOChao He, Tadeusz Kwasniewski. ccece 2012: 1-4 [doi]

2009

2008

Phase Noise Simulation and Modeling of ADPLL by SystemVerilogTingjun Wen, Tadeusz Kwasniewski. bmas 2008: 29-34 [doi]

2007

Design Considerations for a Direct RF Sampling MixerDianyong Chen, Wei Wang, Tadeusz Kwasniewski. tcas, 54-II(11):934-938, 2007. [doi]

Dual Mode K-Best MIMO Detector Architecture and VLSI ImplementationRamin Shariat-Yazdi, Tadeusz Kwasniewski. icecsys 2007: 735-738 [doi]

2005

Behavioral test benches for digital clock and data recovery circuits using Verilog-AS. I. Ahmed, Kent Orthner, Tadeusz Kwasniewski. cicc 2005: 297-300 [doi]

Design considerations for 2nd-order and 3rd-order bang-bang CDR loopsShoujun Wang, HaiTao Mei, Mashkoor Baig, William Bereza, Tadeusz Kwasniewski, Rakesh H. Patel. cicc 2005: 317-320 [doi]

2001

A 1.25-GHz 0.35-/spl mu/m monolithic CMOS PLL based on a multiphase ring oscillatorLizhong Sun, Tadeusz Kwasniewski. jssc, 36(6):910-916, 2001. [doi]

1997

CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communicationsManop Thamsirianunt, Tadeusz Kwasniewski. jssc, 32(10):1511-1524, 1997. [doi]

1995

CMOS high-speed dual-modulus frequency divider for RF frequency synthesisNavid Foroudi, Tadeusz Kwasniewski. jssc, 30(2):93-100, February 1995. [doi]

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