Vinoo Srinivasan - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 11 from 11

2000

A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device ArchitecturesSriram Govindarajan, Vinoo Srinivasan, Preetham Lakshmikanthan, Ranga Vemuri. vlsid 2000: 212-219 [doi]

Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency ConstraintsPreetham Lakshmikanthan, Sriram Govindarajan, Vinoo Srinivasan, Ranga Vemuri. ipps 2000: 924-931 [doi]

1999

Interconnect Synthesis for Reconfigurable Multi-FPGA ArchitecturesVinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri, Jeffrey Walrath. ipps 1999: 588-596

Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA ArchitecturesVinoo Srinivasan, Ranga Vemuri. fccm 1999: 272 [doi]

Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA ArchitecturesVinoo Srinivasan, Ranga Vemuri. fpga 1999: 253 [doi]

1998

1996

Rapid Prototyping of Reconfigurable CoprocessorsNaren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri. asap 1996: 303-312 [doi]

Hierarchical behavioral partitioning for multicomponent synthesisVinoo Srinivasan, Nand Kumar, Ranga Vemuri. eurodac 1996: 212-217 [doi]

Sign in or sign up to see more results.

runs on WebDSL