Vivek K. De - researchr alias

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Viewing Publication 1 - 21 from 21

2022

An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOSRaghavan Kumar, Vikram B. Suresh, Mark A. Anders 0001, Steven K. Hsu, Amit Agarwal 0001, Vivek K. De, Sanu K. Mathew. isscc 2022: 1-3 [doi]

2017

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOSSudhir Satpathy, Sanu K. Mathew, Vikram Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek K. De. jssc, 52(4):940-949, 2017. [doi]

2015

Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI DesignVivek K. De, Andrew B. Kahng, Tanay Karnik, Bao Liu, Milad Maleki, Lu Wang. jetc, 12(3):21, 2015. [doi]

2013

A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop ToleranceKeith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, James W. Tschanz. jssc, 48(4):907-916, 2013. [doi]

Adaptive and Resilient Circuits for Dynamic Variation ToleranceKeith A. Bowman, Carlos Tokunaga, James W. Tschanz, Tanay Karnik, Vivek K. De. dt, 30(6):8-17, 2013. [doi]

2012

A 22nm dynamically adaptive clock distribution for voltage droop toleranceKeith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, Jim Tschanz. vlsic 2012: 94-95 [doi]

2011

A 45 nm Resilient Microprocessor Core for Dynamic Variation ToleranceKeith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De. jssc, 46(1):194-208, 2011. [doi]

All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock ControlKeith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De. tcas, 58-I(9):2017-2025, 2011. [doi]

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS ProcessorSaurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar. jssc, 46(1):184-193, 2011. [doi]

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power ScalingJason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart. jssc, 46(1):173-183, 2011. [doi]

Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM ArraysArijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De. jssc, 46(4):797-805, 2011. [doi]

2009

2008

2007

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect SchemeMaged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek K. De. vlsi, 2007, 2007. [doi]

2004

Low-voltage-swing monolithic dc-dc conversionVolkan Kursun, Siva G. Narendra, Vivek K. De, Eby G. Friedman. tcas, 51-II(5):241-248, 2004. [doi]

1994

Short channel models and scaling limits of SOI and bulk MOSFETsBhavna Agrawal, Vivek K. De, Joseph M. Pimbley, James D. Meindl. jssc, 29(2):122-125, February 1994. [doi]

1993

Analytical drain current models for AlGaAs/GaAs MODFET's including subthreshold conductionVivek K. De, James D. Meindl. jssc, 28(5):596-604, May 1993. [doi]

An analytical threshold voltage and subthreshold current model for short-channel MESFETsVivek K. De, James D. Meindl. jssc, 28(2):169-172, February 1993. [doi]

An analytical threshold voltage and subthreshold current model for short-channel AlGaAs/GaAs MODFETsVivek K. De, James D. Meindl. jssc, 28(2):180-183, February 1993. [doi]

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