By entering into the ultra deep sub-micron (UDSM) era, the role played by the on-chip communication system is getting more and more relevance. In fact, as technology shrinks, gates become faster and more power efficient whereas wires become slower and more power hungry. Thus, the on-chip communication system represents one of the most important elements which determine the overall performance, cost, reliability, and energy consumption of a modern multi-processor system-on-chip (MPSoC). If the raw computation horsepower seems to be unlimited thanks to the ability of instancing more and more cores in a single silicon die, scalability issues, due to the need of making efficient and reliable the communication between the increasing number of cores, becomes the real problem.
Several phenomena like communication errors (due to crosstalk, electromagnetic interference, intersymbol interference, etc.), link latency, link power dissipation, etc., that were considered negligible in the previous technologies, are dominant in current and next generation MPSoC. The network-on-chip (NoC) paradigm is considered as the most viable solution for designing on-chip communication systems able to tackle with the above issues.
The goal of the workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. This workshop will focus on issues related to design, analysis and testing of on-chip networks.
| Submissions: | September 12, 2012 |
| Notification: | October 22, 2012 |
| Event: | December 1, 2012-December 2, 2012 |