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2019

29th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2019, Rhodes, Greece, July 1-3, 2019IEEE, 2019. [doi]

One-Hot Residue Logarithmic Number SystemsMark G. Arnold, Ioannis Kouretas, Vassilis Paliouras, Austin Morgan. patmos 2019: 97-102 [doi]

Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point MultiplierTaiYu Cheng, Jaehoon Yu, Masanori Hashimoto. patmos 2019: 91-96 [doi]

Temperature-aware writing architecture for multilevel memristive cellsAmadeo de Gracia Herranz, Marisa López-Vallejo. patmos 2019: 57-62 [doi]

On the Static CMOS Implementation of Magnitude ComparatorsCostas Efstathiou, Yiorgos Tsiatouhas. patmos 2019: 103-106 [doi]

Morphological Reservoir Computing HardwareFabio Galán-Prado, Joan Font-Rosselló, Josep L. Rosselló. patmos 2019: 141-144 [doi]

Stochastic Radial Basis Neural NetworksFabio Galán-Prado, Alejandro Morán, Joan Font, Miquel Roca, Josep L. Rosselló. patmos 2019: 145-149 [doi]

UVM-based Verification of a Digital PLL Using SystemVerilogNikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos. patmos 2019: 23-28 [doi]

Energy Efficient Clock Distribution with Low-Leakage Multi-Vt BuffersAnil Kumar Gundu, Volkan Kursun. patmos 2019: 113-118 [doi]

Reliability of an Industrial Wireless Communication System using Approximate UnitsMingjie Hao, Ardalan Najafi, Alberto García Ortiz, Ludwig Karsthof, Steffen Paul, Jochen Rust. patmos 2019: 87-90 [doi]

Implementing VESA Display Stream Compression Encoder in FPGAsNikolaos Kefalas, George Theodoridis. patmos 2019: 35-40 [doi]

RISC-V Extensions for Bit Manipulation InstructionsBastian Koppelmann, Peer Adelt, Wolfgang Mueller, Christoph Scheytt. patmos 2019: 41-48 [doi]

Radix-3 low-complexity modulo-M multipliersIoannis Kouretas, Vassilis Paliouras. patmos 2019: 107-112 [doi]

High Performance Accelerator for CNN ApplicationsAngelos Kyriakos, Vasileios Kitsakis, Alexandros Louropoulos, Elissaios-Alexios Papatheofanous, Ioannis Patronas, Dionysios I. Reisis. patmos 2019: 135-140 [doi]

Modelling Reversion Loss and Shoot-through Current in Switched-Capacitor DC-DC Converters with Petri NetsDanhui Li, Fei Xia, Junwen Luo, Alex Yakovlev. patmos 2019: 69-74 [doi]

Process Variation-Aware Analytical Modeling of Subthreshold Leakage PowerAnala M., B. P. Harish. patmos 2019: 119-124 [doi]

A Calibration Procedure for Sensor Based Adaptive Voltage Scaling ApproachesChristoph Niemann, Munawar Ali, Jakob Heller, Dirk Timmermann. patmos 2019: 81-86 [doi]

Smart sensor system for leakage detection in pipes carrying oil products in noisy environment: The ESTHISIS ProjectSpiros Nikolaidis, Dimitrios Porlidas, George-Othon Glentis, Anestis Kalfas, Christos Spandonidis. patmos 2019: 125-126 [doi]

A Synergy of a Closed-Loop DVFS Controller and CPU Hot-Plug For Run-Time Thermal Management in Multicore SystemsMichail Noltsis, Nikolaos Zambelis, Francky Catthoor, Dimitrios Soudris. patmos 2019: 49-56 [doi]

Adaptive Transient Computing for Power-Neutral Embedded DevicesCarl Christian Rheinländer, Norbert Wehn. patmos 2019: 63-68 [doi]

A High-Performance Neuron for Artificial Neural Network based on Izhikevich modelMaria Sapounaki, Athanasios Kakarountas. patmos 2019: 29-34 [doi]

Simulation-based Verification of the Youngest-First Round-Robin Core Gating PatternAleksandar Simevski, Milos Krstic. patmos 2019: 150-157 [doi]

Design of a flexible multi-source energy harvesting system for autonomously powered IoT : The PERPS projectStelios Siskos, V. Gogolou, C. Tsamis, A. Kerasidou, Gregory Doumenis, K. Tsiapali, Serafeim Katsikas, Andreas Sakellariou. patmos 2019: 133-134 [doi]

Multi-Armed Bandits for Autonomous Timing-driven Design OptimizationApostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos. patmos 2019: 17-22 [doi]

Voltage Scaling and Guardband Customization of Multiple Constituent Components in SoC-FPGAIoannis Stratakos, Konstantinos Maragos, George Lentaris. patmos 2019: 75-80 [doi]

Impact of Coarse-Grained Power Gate Placement on a Fine-Grained System DesignShylesh Umapathy, Aaron Stillmaker. patmos 2019: 158-162 [doi]

Graph-Based STA for Asynchronous ControllersNikolaos Xiromeritis, Stavros Simoglou, Christos P. Sotiriou, Nikolaos Sketopoulos. patmos 2019: 9-16 [doi]

The Involution Tool for Accurate Digital Timingand Power AnalysisDaniel Öhlinger, Jürgen Maier 0002, Matthias Függer, Ulrich Schmid 0001. patmos 2019: 1-8 [doi]

2018

28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, Platja d'Aro, Spain, July 2-4, 2018IEEE, 2018. [doi]

Model-Free Runtime Management of Concurrent Workloads for Energy-Efficient Many-Core Heterogeneous SystemsAli Aalsaud, Ashur Rafiev, Fei Xia, Rishad A. Shafik, Alex Yakovlev. patmos 2018: 206-213 [doi]

MEMS-Based Runtime Idle Energy Minimization for Bursty Workloads in Heterogeneous Many-Core SystemsAli Aalsaud, Haider Alrudainy, Rishad A. Shafik, Fei Xia, Alex Yakovlev. patmos 2018: 198-205 [doi]

A Multi-Level Power-on Reset for Fine-Grained Power ManagementAndres Amaya, Luis E. Rueda G, Elkim Roa. patmos 2018: 129-132 [doi]

Mobile Terminals System-Level Memory Exploratio for Power and Performance OptimizationAmal Ben Ameur, Michel Auguin, François Verdier, Valerio Frascolla. patmos 2018: 23-28 [doi]

Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCsP. Anagnostou, A. Gomez, Pascal A. Hager, Hamed Fatemi, José Pineda de Gyvez, Lothar Thiele, Luca Benini. patmos 2018: 54-61 [doi]

A 40nm Critical Path Monitor for the Detection of Setup and Hold Time ViolationsHernan Aparicio, Pablo Ituero. patmos 2018: 13-18 [doi]

A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID ApplicationsAsghar Bahramali, Marisa López-Vallejo. patmos 2018: 62-67 [doi]

Exploiting Temporal Misalignment to Optimize the Interconnect Performance for 3D IntegrationLennart Bamberg, Alberto García Ortiz. patmos 2018: 214-221 [doi]

Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual ChannelsLennart Bamberg, Jan Moritz Joseph, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz. patmos 2018: 222-228 [doi]

Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI TechnologyEnrique Barajas, Xavier Aragonès, Diego Mateo, Francesc Moll, Antonio Rubio, Javier Martín-Martínez, Rosana Rodríguez, Marc Porti, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández. patmos 2018: 82-87 [doi]

Hardware Implementation of a Low-Power K-Best MIMO Detector Based on a Hybrid Merge NetworkIbrahim A. Bello, Basel Halak, Mohammed El-Hajjar, Mark Zwolinski. patmos 2018: 191-197 [doi]

Multiclass Network Attack Classifier Using CNN Tuned with Genetic AlgorithmsRoberto Blanco, Pedro Malagón, Juan J. Cilla, José Manuel Moya. patmos 2018: 177-182 [doi]

VCO Verilog AMS Model for Fast Simulation in VCO-Based ADCDavid Buffeteau, Dominique Morche, Jose-Luis Gonzalez Jimenez. patmos 2018: 19-22 [doi]

Testing Framework for in-Hardware Verification of the Hardware Modules Generated Using HLSJulian Caba, Fernando Rincón, Julio Dondo, Jesús Barba, Manuel J. Abaldea, Juan Carlos López. patmos 2018: 103-110 [doi]

Enhanced RF Harvesting System by the Utilization of Resonant CavitiesGuillem Martinez de Arriba, Ertugrul Coskuner, Joan J. Garcia-Garcia. patmos 2018: 29-31 [doi]

A Battery-Less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power TransferRemi Dekimpe, Pengcheng Xu, Maxime Schramme, Denis Flandre, David Bol. patmos 2018: 68-75 [doi]

Ultra-Low Power Subthreshold Quasi Floating Gate CMOS Logic Family for Energy HarvestingM. Pilar Garde, Antonio J. López-Martín, Daniel Orradre, Jaime Ramírez-Angulo. patmos 2018: 118-122 [doi]

UVM-Based Verification of a Mixed-Signal Design Using SystemVerilogNikolaos Georgoulopoulos, Ioannis Giannou, Alkiviadis A. Hatzopoulos. patmos 2018: 97-102 [doi]

Memory Access Pattern Profiling for Streaming Applications Based on MATLAB ModelsThomas Goldbrunner, Thomas Wild, Andreas Herkersdorf. patmos 2018: 32-38 [doi]

Evaluation of an Artificial Neural Network Approach for Timing Modeling of CMOS GatesSotirios K. Goudos, Nikolaos Karagiorgos, Maria Ntogramatzi, Ioannis Messaris, Spyridon Nikolaidis. patmos 2018: 169-176 [doi]

Blade-OC Asynchronous Resilient Template ‡ This research has been supported in part by NSF Grant #1619415Moisés Herrera, Tingyu Wang, Peter A. Beerel. patmos 2018: 147-154 [doi]

Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage VariabilityA. K. M. Mahfuzul Islam, Hidetoshi Onodera. patmos 2018: 140-146 [doi]

Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT DevicesRuzica Jevtic, Marko Ylitolva, Lauri Koskinen. patmos 2018: 243-247 [doi]

Hierarchical Timing-Critical Paths Analysis in Sequential CircuitsLembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin. patmos 2018: 1-6 [doi]

Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy ManagementRida Kheirallah, Jean Marc Galliere, Nadine Azémard, Gilles R. Ducharme. patmos 2018: 88-91 [doi]

A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level DesignsJohannes Knödtel, Wolffhardt Schwabe, Tobias Lieske, Marc Reichenbach, Dietmar Fey. patmos 2018: 46-53 [doi]

VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic DesignSachin Maheshwari, Vivian A. Bartlett, Izzet Kale. patmos 2018: 111-117 [doi]

A Reliable PUF in a Dual Function SRAMMohd Syafiq Mispan, Shengyu Duan, Basel Halak, Mark Zwolinski. patmos 2018: 76-81 [doi]

Backlight Compensation Algorithms to Improve Power Consumption in LED- LCD DisplaysKonstantinos Oikonomou, Orestis Theodorakopoulos, Georgios Keramidas, Georgios Theodoridis. patmos 2018: 254-260 [doi]

Quantitative Evaluation of Certain SET Mitigation Techniques for Multiply-Accumulate Circuits and State MachinesVassilis Paliouras, Konstantina Karagianni, Yann Oster. patmos 2018: 183-190 [doi]

FPGA-Based Platform for Fast Accurate Evaluation of Ultra Low Power SoCGuillaume Patrigeon, Pascal Benoit, Lionel Torres. patmos 2018: 123-128 [doi]

Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard ApplicationsHimadri Singh Raghav, Vivian A. Bartlett, Izzet Kale. patmos 2018: 39-45 [doi]

Optical and Electrical Simulations of Radiation-Hard Photodiode in 0.35μM High-Voltage CMOS TechnologyFilip Segmanovic, Frederic Roger, Gerald Meinhard, Ingrid Jonak-Auer, Tomislav Suligoj. patmos 2018: 92-96 [doi]

Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA DesignsRoberto Sierra, Carlos Carreras, Gabriel Caffarena. patmos 2018: 7-12 [doi]

Reservoir Computing Hardware for Time Series ForecastingErik S. Skibinsky-Gitlin, Miquel L. Alomar, Eugeni Isern, Miquel Roca, Vincent Canals, Josep L. Rosselló. patmos 2018: 133-139 [doi]

Effect of Temperature Variation in Experimental DPA and DEMA AttacksErica Terra-Sanchez, Antonio J. Acosta. patmos 2018: 163-168 [doi]

A Systematic Performance Comparison of Ultra Low-Power AES S-BoxesThomas Vandenabeele, Roel Uytterhoeven, Wim Dehaene, Nele Mentens. patmos 2018: 248-253 [doi]

Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory StructureHongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera. patmos 2018: 237-242 [doi]

Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor DesignsMonir Zaman, Mustafa M. Shihab, Ayse K. Coskun, Yiorgos Makris. patmos 2018: 229-236 [doi]

TSV Assignment of Thermal and Wirelength Optimization for 3D-IC RoutingYi Zhao, Cong Hao, Takeshi Yoshimura. patmos 2018: 155-162 [doi]

2017

27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017, Thessaloniki, Greece, September 25-27, 2017IEEE, 2017. [doi]

Approximate adder segmentation technique and significance-driven error correctionKhaled Al-Maaitah, Ghaith Tarawneh, Ahmed Soltan, Issa Qiqieh, Alex Yakovlev. patmos 2017: 1-6 [doi]

An FPGA-based thermal emulation framework for multicore systemsMd Shahidul Alam, Alberto García Ortiz. patmos 2017: 1-6 [doi]

Edge effect aware crosstalk avoidance technique for 3D integrationLennart Bamberg, Amir Najafi, Alberto García Ortiz. patmos 2017: 1-8 [doi]

Memristive two-portsDalibor Biolek, Zdenek Biolek, Viera Biolkova. patmos 2017: 1-4 [doi]

Pulse controlled memristor-based delay elementThanasin Bunnam, Ahmed Soltan, Danil Sokolov, Alex Yakovlev. patmos 2017: 1-8 [doi]

Evaluation and analysis of single-phase clock flip-flops for NTV applicationsYunpeng Cai, Anand Savanth, Pranay Prabhat, James Myers, Alex S. Weddell, Tom J. Kazmierski. patmos 2017: 1-6 [doi]

An analytical delay model for ReRAM memory cellsCarol de Benito, Mohamed Moner Al Chawa, Josep L. Rosselló, Miquel Roca, Rodrigo Picos, Ioannis Messaris, Spiridon Nikolaidis. patmos 2017: 1-6 [doi]

Capacitive adiabatic logic based on gap-closing MEMS devicesAyrat Galisultanov, Yann Perrin, Hatem Samaali, Louis Hutin, Hervé Fanet, Philippe Basset, Gaël Pillonnet. patmos 2017: 1-6 [doi]

Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICsLeonidas Katselas, Hailong Jiao, Angelos Athanasiadis, Christos Papameletis, Alkis A. Hatzopoulos, Erik Jan Marinissen. patmos 2017: 1-8 [doi]

High-throughput FPGA implementation of the CCSDS 122.0-B-1 compression standardNikolaos Kefalas, George Theodoridis. patmos 2017: 1-8 [doi]

Timing modeling at RT-level by separation of design- and stress related aging impactsNils Koppaetzky, Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel. patmos 2017: 1-6 [doi]

Rapid power-management exploration using post-processing of the system-level simulation resultsDominik Macko. patmos 2017: 1-6 [doi]

Effect of supply voltage on random telegraph noise of transistors under switching conditionIslam A. K. M. Mahfuzul, Hidetoshi Onodera. patmos 2017: 1-8 [doi]

User dependent aging prediction model for automotive controllers with power electronicsSunil Malipatlolla, Ahmet Unutulmaz, Domenik Helms, Wolfgang Nebel. patmos 2017: 1-6 [doi]

From edge to cloud: Design and implementation of a healthcare Internet of Things infrastructureDimosthenis Masouros, Ioannis Bakolas, Vasileios Tsoutsouras, Kostas Siozios, Dimitrios Soudris. patmos 2017: 1-6 [doi]

Energy aware Networks-on-Chip cortex inspired communicationErwan Moreac, Johann Laurent, Pierre Bomel, André Rossi, Emmanuel Boutillon, Maurizio Palesi. patmos 2017: 1-8 [doi]

A fair comparison of adders in stochastic regimeArdalan Najafi, Moritz Weisbrich, Guillermo Payá Vayá, Alberto García Ortiz. patmos 2017: 1-6 [doi]

Optimal content-dependent dynamic brightness scaling for OLED displaysDaniele Jahier Pagliari, Enrico Macii, Massimo Poncino. patmos 2017: 1-6 [doi]

Placement-based SER estimation in the presence of multiple faults in combinational logicGeorgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Nestor E. Evmorfopoulos, George Dimitriou, Georgios I. Stamoulis. patmos 2017: 1-6 [doi]

Robustness of power analysis attack resilient adiabatic logic: WCS-QuAL under PVT variationsHimadri Singh Raghav, Vivian A. Bartlett, Izzet Kale. patmos 2017: 1-8 [doi]

Optical sensor process variability in a 0.18 μm high voltage CMOS technologyFrederic Roger, Anderson Pires Singulani, Jong Mun Park. patmos 2017: 1-6 [doi]

Human α-thrombin detection platform using aptamers on a silicon nanowire field-effect transistorLotta Romhildt, Felix Zorgiebel, Bergoi Ibarlucea, Maryam Vahdatzadeh, Larysa Baraban, Gianaurelio Cuniberti, Sebastian Pregl, Walter M. Weber, Thomas Mikolajick, Jörg Opitz. patmos 2017: 1-4 [doi]

Fault-tolerant routing methodology for Networks-on-ChipS. Savva. patmos 2017: 1-3 [doi]

3DBUFFBLESS: A novel buffered-bufferless hybrid router for 3D Networks-on-ChipKonstantinos Tatas, S. Savva, Costas Kyriacou. patmos 2017: 1-8 [doi]

Modeling energy-performance tradeoffs in ARM big.LITTLE architecturesEvangelos Vasilakis, Ioannis Sourdis, Vassilis Papaefstathiou, Antonis Psathakis, Manolis G. H. Katevenis. patmos 2017: 1-8 [doi]

High voltage recycling scheme to improve power consumption of regulated charge pumpsSteve Ngueya W., Julien Mellier, Stephane Ricard, Jean Michel Portal, Hassen Aziza. patmos 2017: 1-5 [doi]

FLINT+: A runtime-configurable emulation-based stochastic timing analysis frameworkMoritz Weisbrich, Guillermo Payá Vayá, Lukas Gerlach, Holger Blume, A. Najafi, Alberto García Ortiz. patmos 2017: 1-8 [doi]

Power proportional adder design for Internet of Things in a 65 nm processAdrian Wheeldon, Jordan Morris, Danil Sokolov, Alex Yakovlev. patmos 2017: 1-6 [doi]

Parasitic effects on memristive logic architectureXiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir. patmos 2017: 1-5 [doi]

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